Datasheet

Intel
®
Xeon
®
Processor C5500/C3500 Series
February 2010 Datasheet, Volume 1
Order Number: 323103-001 153
PCI Express Non-Transparent Bridge
The address forwarded from one interface to the other is translated by adding a base
address to the offset within the BAR that the address belongs to as shown in Figure 56.
PCI Express utilizes both 32-bit and 64-bit address schemes via the 3DW and 4DW
headers. To prevent address aliasing, all devices must decode the entire address range.
All discussions in this section refer to 64-bit addressing. If the 3DW header is used the
upper 32-bits of address are assumed to be 0000_0000h.
The NTB allows external PCI Express requesters to access memory space via address
routed TLPs. The PCI Express requesters can read or write NTB memory-mapped
registers or Intel
®
Xeon
®
processor C5500/C3500 series local memory space. The
process of inbound/outbound address translation involves two steps:
• Address Detection Inbound/Outbound
— Test to see if the PCI address is within the base and limit registers defined for
BAR 2/3, 4/5.
— If the address is outside of the window defined by the base and limit registers,
the transaction will be terminated as an unsupported request (UR).
• Address Translation
— Inbound with VT-d2 turned off.
• Translate a remote address to a local physical address.
— Inbound with VT-d2 turned on.
• Translate a remote address to a local guest physical address that is then
forwarded to the VT-d2 logic. The VT-d2 logic then converts the guest
physical address to a host physical address.
—Outbound:
• Translate a local physical address to a remote guest address.
Figure 56. Direct Address Translation