Datasheet
Intel
®
Xeon
®
Processor C5500/C3500 Series
February 2010 Datasheet, Volume 1
Order Number: 323103-001 151
PCI Express Non-Transparent Bridge
— It is the responsibility of the remote host system to introduce the Intel
®
Xeon
®
processor C5500/C3500 series NTB into its hierarchy and is outside the scope
of this document to describe that procedure.
— If the attached system is another Intel
®
Xeon
®
processor C5500/C3500 series
RP the EP is brought into the system as described in Case 1 above.
— When Intel
®
Xeon
®
processor C5500/C3500 series NTB is powered on and gets
to enumeration, it finds its internal RCiEP and stop with respect to that port.
— When the link trains, Intel
®
Xeon
®
processor C5500/C3500 series NTB logic
generates a host link up event.
— Next, a software configured and hardware generated “heartbeat”
communication is setup between the two systems. The heartbeat is a periodic
doorbell sent in both directions as an indication to software that each side
sending the heartbeat is alive and ready for sending and receiving transactions.
Note: When the link goes up/down a “link up/down” event is issued to the local Intel
®
Xeon
®
processor C5500/C3500 series host in the same silicon as the NTB. When the link goes
down the heartbeat will also be lost and all communications will be halted. Before
communications are started again software must receive notification of both link up
event and heartbeat from the remote link partner.
•Intel
®
Xeon
®
processor C5500/C3500 series NTB powered and enumerated before
remote RP is powered on.
• The local host containing the Intel
®
Xeon
®
processor C5500/C3500 series NTB will
power on and enumerate its devices. The NTB it will be discovered as RCiEP.
— At this point the Intel
®
Xeon
®
processor C5500/C3500 series is waiting for a
link up event and heartbeat before sending any transactions to the NTB port.
— Sometime later the remote host connected through the remote RP is powered
on and enumerated. When enumeration software gets to the NTB it will
discover a PCIE EP.
— The remote system will then setup and send a periodic heartbeat message.
Once heartbeat and linkup are valid on each side communications can then be
sent between the systems.
Case 3: Intel
®
Xeon
®
processor C5500/C3500 series NTB connected to Intel
®
Xeon
®
processor C5500/C3500 series NTB
• It does not matter which side is powered on first. One side will power on,
enumerate and find the internal RCiEP and then wait for link up event and a
heartbeat message.
• Sometime later the system on the other side of the link is powered on and
enumerated. Since it is also a NTB, it will find the internal RCiEP, and then wait for
link up event and a heartbeat message.
• Now both systems are powered on and link training is started.
• Upon detection of the link up event, both sides will send a link up interrupt to their
respective host.
• Both sides independently, will then setup and start sending a periodic heartbeat
messages across the link.
• Once periodic heartbeat is detected by each system, it is ready for
communications.