Datasheet
PCI Express Non-Transparent Bridge
Intel
®
Xeon
®
Processor C5500/C3500 Series
Datasheet, Volume 1 February 2010
150 Order Number: 323103-001
3. Enumeration SW running independently on each host will discover and set the base
address pointer for both primary BAR2/3 and primary BAR4/5 registers
(PB23BASE, PB45BASE) of the NTB associated with that same host. At this point all
that is known is the size and location of the memory window. E.g. 4KB to 512GB
prefetchable memory window placed on a size multiple base address.
In the B2B case the memory map region that is common to the secondary side of both
of the NTBs does not map to either system address map. It is only used as a
mechanism to pass transactions from one NTB to the other. The requirements for this
no mans land between the endpoints, is that both sides of the link must be set to the
same memory window (size multiple) and must be aligned on the same base address
for the associated bar.
Note: The reset default values for SB23BASE Section 3.20.2.12, and PBAR2XLAT
Section 3.21.1.3, have been set to a default value of 256 GB, SB45BASE
Section 3.20.2.13 and PBAR4XLAT Section 3.21.1.4 have been set to a default value of
512 GB. This provides ability to support sizes up to 256 GB window for SB23BASE and
sizes up to 512 GB window for SB45BASE.
4. As a final configuration setup during run time operation the translate registers are
setup by the local host associated with the physical NTB to map the transactions
into the local system memory associated the respective NTB receiving the
transactions. These are the SBAR2XLAT Section 3.21.1.7 and SBAR4XLAT
Section 3.21.1.8 registers.
3.6.5 Enumeration and Power Sequence
Having a PCIE port that is configurable as a RP or NTB opens up additional possibilities
for system level layout. For instance the second system could be on another blade in
the same rack or in a separate rack all together. This design is flexible in how the
system comes up regarding power cycling of the individual systems but the effects
must be stated so that the end user understands what steps must be taken in order to
get the two systems to communicate.
Case 1: Intel
®
Xeon
®
processor C5500/C3500 series Root Port (RP) connected to
remote Endpoint (EP)
• Powered on at same time:
Since Intel
®
Xeon
®
processor C5500/C3500 series and the attached EP are
powered on at the same time enumeration will complete as expected.
• EP powered on after Intel
®
Xeon
®
processor C5500/C3500 series RP enumerates:
When the EP is installed a hot plug event is issued in order to bring the EP on line.
Case 2: Intel
®
Xeon
®
processor C5500/C3500 series NTB connected to remote RP
• Powered on at same time:
—Intel
®
Xeon
®
processor C5500/C3500 series NTB will enumerate and see the
primary side of the NTB. The device will be seen as a RCiEP.
— The remote host connected through the remote RP will enumerate and see the
secondary side of the NTB. The device will be seen as a PCIE EP.
• Remote host connected through the remote RP is powered and enumerated before
the Intel
®
Xeon
®
processor C5500/C3500 series NTB is powered on.
— When the remote host goes through enumeration it will probe the RP connected
to the NTB and find no device. (NTB is still powered off)
— Sometime later, the Intel
®
Xeon
®
processor C5500/C3500 series NTB is
powered on.