Datasheet
Intel
®
Xeon
®
Processor C5500/C3500 Series
February 2010 Datasheet, Volume 1
Order Number: 323103-001 15
12.1.2.2 DDR Channel B Signals.......................................................... 420
12.1.2.3 DDR Channel C Signals.......................................................... 421
12.1.2.4 System Memory Compensation Signals .................................... 421
12.1.3 PCI Express* Signals ............................................................................ 422
12.1.4 Processor SMBus Signals....................................................................... 422
12.1.5 DMI / ESI Signals................................................................................. 423
12.1.6 Clock Signals....................................................................................... 423
12.1.7 Reset and Miscellaneous Signals............................................................. 424
12.1.8 Thermal Signals ................................................................................... 424
12.1.9 Processor Core Power Signals ................................................................ 425
12.1.10Power Sequencing Signals..................................................................... 426
12.1.11No Connect and Reserved Signals........................................................... 426
12.1.12ITP Signals.......................................................................................... 427
12.2 Physical Layout and Signals.............................................................................. 427
13.0 Electrical Specifications......................................................................................... 483
13.1 Processor Signaling ......................................................................................... 483
13.1.1 Intel
®
QuickPath Interconnect ............................................................... 483
13.1.2 DDR3 Signal Groups ............................................................................. 483
13.1.3 Platform Environmental Control Interface (PECI) ...................................... 484
13.1.3.1 Input Device Hysteresis ......................................................... 484
13.1.4 PCI Express/DMI.................................................................................. 484
13.1.5 SMBus Interface................................................................................... 485
13.1.6 Clock Signals....................................................................................... 486
13.1.7 Reset and Miscellaneous........................................................................ 486
13.1.8 Thermal.............................................................................................. 486
13.1.9 Test Access Port (TAP) Signals ............................................................... 486
13.1.10Power / Other Signals........................................................................... 486
13.1.10.1 Power and Ground Lands ....................................................... 487
13.1.10.2 Decoupling Guidelines............................................................ 487
13.1.10.3 Processor VCC Voltage Identification (VID) Signals .................... 487
13.1.10.4 Processor VTT Voltage Identification (VTT_VID) Signals.............. 494
13.1.11Reserved or Unused Signals................................................................... 495
13.2 Signal Group Summary.................................................................................... 495
13.3 Mixing Processors............................................................................................ 500
13.4 Flexible Motherboard Guidelines (FMB)............................................................... 500
13.5 Absolute Maximum and Minimum Ratings ........................................................... 500
13.6 Processor DC Specifications .............................................................................. 501
13.6.1 VCC Overshoot Specifications................................................................. 507
13.6.2 Die Voltage Validation........................................................................... 508
13.6.3 DDR3 Signal DC Specifications............................................................... 508
13.6.4 PCI Express Signal DC Specifications....................................................... 510
13.6.5 SMBus Signal DC Specifications.............................................................. 511
13.6.6 PECI Signal DC Specifications................................................................. 512
13.6.7 System Reference Clock Signal DC Specifications...................................... 512
13.6.8 Reset and Micscellaneous DC Specifications ............................................. 513
13.6.9 Thermal DC Specification....................................................................... 513
13.6.10Test Access Port (TAP) DC Specification................................................... 514
13.6.11Power Sequencing Signal DC Specification ............................................... 514
14.0 Testability ............................................................................................................. 515
14.1 Boundary-Scan............................................................................................... 515
14.2 TAP Controller Operation and State Diagram....................................................... 515
14.3 TAP Instructions and Opcodes........................................................................... 517
14.3.1 Processor Core TAP Controller................................................................ 517
14.3.2 Processor Un-Core TAP Controller........................................................... 517