Datasheet
Intel
®
Xeon
®
Processor C5500/C3500 Series
February 2010 Datasheet, Volume 1
Order Number: 323103-001 149
PCI Express Non-Transparent Bridge
strap input PE_NTBXL is disabled and has no meaning. User should leave the PE_NTBXL
pin strap unconnected in this configuration to save board space.
Note: PPD, Crosslink Configuration Status field has been provided as a means to visually see
the polarity of the final result between the pin strap and the BIOS option.
3.6.4 B2B BAR and Translate Setup
When connecting two memory systems via B2B NTBs there is a requirement to match
memory windows on the secondary side of the NTBs between the two systems. The
registers that accomplish this are the primary bar translate registers and the secondary
bar base registers on both of the connected NTBs as shown in Figure 54.
The following text explains the steps that go along with Figure 54 and assumes that we
have already pre-configured the platforms for B2B operation and two memory windows
in each direction. See Section 3.6.1, ““A Priori” Configuration Knowledge” for how to
accomplish pre-boot configuration.
1. Host A and Host B power up independently (no required order).
2. Once each system has powered up and released control to the NTB to train the link
will proceed to the L0 state (Link up).
Figure 54. B2B BAR and Translate Setup
HOST B
NTB
HOST A
NTB
PB23BASE PBAR2XLAT SB23BASE SBAR2XLAT
Reset Default
256G
Reset Default
256G
Configured by
Host A
Configured by
Host B
PB45BASE PBAR4XLAT SB45BASE SBAR4XLAT
Reset Default
512G
Reset Default
512G
Configured by
Host A
Configured by
Host B
SAME
SAME
SBAR2XLAT SB23BASE PBAR2XLAT PB23BASE
Reset Default
256G
Reset Default
256G
Configured by
Host A
Configured by
Host B
SBAR4XLAT SB45BASE PBAR4XLAT PB45BASE
Reset Default
512G
Reset Default
512G
Configured by
Host A
Configured by
Host B
SAME
SAME
HOST A
TO
HOST B
HOST B
TO
HOST A