Datasheet
PCI Express Non-Transparent Bridge
Intel
®
Xeon
®
Processor C5500/C3500 Series
Datasheet, Volume 1 February 2010
148 Order Number: 323103-001
No Cross-link configuration is required: Hardware will automatically strap the port as
an DSD/USP when the PPD register, Port Definition field, is set to “10”b (NTB/RP).
The Intel
®
Xeon
®
processor C5500/C3500 series NTB will train as DSD/USP and the
external RP will train as USD/DSP. No conflict occurs and link training proceeds without
need for crosslink training.
Note: When configured as a NTB/RP. the PE_NTBXL pin should be left as a no-
connect (NTB logic does not look at the state of the PE_NTBXL pin when
configured as a NTB/RP). The PPD Crosslink Control Override field bits 3:2
have no meaning when configured as an NTB/RP.
Case 3: Intel
®
Xeon
®
processor C5500/C3500 series NTB connected to another Intel
®
Xeon
®
processor C5500/C3500 series,
Crosslink configuration is required:
Two options are provided to give the end user flexibility in resolving crosslink in the
case of back to back NTBs.
Option 1:
The first option is to use a pin strap to set the polarity of the port without requiring
BIOS/SW interaction. The Intel
®
Xeon
®
processor C5500/C3500 series has provided
the pin strap “PE_NTBXL” that is strapped at platform level to select the polarity of the
NTB port.
The NTB port is forced to be an USD/DSP when the PE_NTBXL pin is left as no-connect.
The NTB port is forced to be DSD/USP when the PE_NTBXL pin is pulled to ground
through a resistor.
After one of the platforms NTB port is left floating (USD/DSP) and the other platforms
NTB port is pulled to ground (DSD/USP), no conflict occurs and link training proceeds
without need for crosslink training.
This option works as follows.
• Pin strap PE_NTBXL as defined above
• PPD, Port definition field is set to “01”b (NTB/NTB) on both platforms
• BIOS/SW enables the port to start training. (Order of release does not matter)
Option 2:
The second option is to use BIOS/SW to force the polarity of the ports prior to releasing
the port.
This option works as follows.
• PPD, Port definition field is set to “01”b (NTB/NTB) on both platforms
• PPD, Crosslink Control Override is set to “11”b (USD/DSP) on one platform
• PPD, Crosslink Control Override is set to “10”b (DSD/USP) on the other platform
• BIOS/SW enables the port to start training. (Order of release does not matter)
After one of the platforms is forced to be an (USD/DSP) and the other platforms NTB
port is forced to be a (DSD/USP), no conflict occurs and link training proceeds without
need for crosslink training.
Note: When the PPD, Port definition field is set to “01”b (NTB/NTB) and the PPD, Crosslink
control Override field is set to a value of “11”b or “10”b, the functionality of the pin