Datasheet

Intel
®
Xeon
®
Processor C5500/C3500 Series
February 2010 Datasheet, Volume 1
Order Number: 323103-001 145
PCI Express Non-Transparent Bridge
• Header type is set to type 0
The base address registers (BAR) specify the address decode functions that will be
supported by the NTB.
•The Intel
®
Xeon
®
processor C5500/C3500 series NTB will support only 64b BARs.
Intel
®
Xeon
®
processor C5500/C3500 series will not support 32b BARs.
•The Intel
®
Xeon
®
processor C5500/C3500 series NTB will support memory decode
region only. Intel
®
Xeon
®
processor C5500/C3500 series will not support IO
decode region.
— Bit 0 in all Base Address registers is read-only and used to determine whether
the register maps into Memory or I/O Space. Base Address registers that map
to Memory Space must return a 0 in bit 0. Base Address registers that map to
I/O Space must return a 1 in bit 0. The Intel
®
Xeon
®
processor C5500/C3500
series NTB only supports Memory Space so this bit is hard-coded to 0.
— Bits [2:1] of each BAR indicate whether the decoder address is 32b (4GB
memory space) or 64b (>4GB memory space)
00 = Locate anywhere in 32-bit access space
01 = Reserved
10 = Locate anywhere in 64-bit access space
11 = Reserved
Intel
®
Xeon
®
processor C5500/C3500 series only supports 64b BARs so these
bits will be hard-coded to “10”
— Bit[3] of a memory BAR specifies whether the memory is prefetchable or not.
1=Prefetchable Memory
0=Non-Prefetchable
• Primary side BAR 0/1 (internal side of the bridge) is a fixed 64KB prefetchable
memory associated with MMIO space and will be used to map the 256B PCI
configuration space of the secondary side, and the shared MMIO space of the NTB
into the local host memory. Local host will have access to the configuration
registers on primary side of the NTB, the shared MMIO space of the NTB, and the
first 256B of the secondary side of the NTB through memory mapped IO
transactions.
Note: BAR 0/1 Semaphore register has read side effects that must be properly handled by
software
• Secondary side BAR 0/1 (external side of the bridge) is a fixed 32KB programmable
as either prefetchable or non-prefetchable memory associated with configuration
and MMIO space and will be used to map the configuration space of the secondary
side and the shared MMIO space of the NTB into the remote host memory. The
remote host will have access to the configuration registers on the secondary side of
the NTB and the shared MMIO space of the NTB through memory mapped IO
transactions. The remote host cannot see the configuration registers on the
primary side of the bridge.
• BAR 2/3 and BAR 4/5 will provide two BARs for memory windows. These BARs will
be for prefetchable memory only.
•Intel
®
Xeon
®
processor C5500/C3500 series will not support BARs for IO space.
Table 79. Class Code
23:16 15:8 7:0
Class Code Sub-Class Code Programming Interface Byte
0x06 (bridge) 0x80 (other bridge type) 0x00