Datasheet

PCI Express Non-Transparent Bridge
Intel
®
Xeon
®
Processor C5500/C3500 Series
Datasheet, Volume 1 February 2010
144 Order Number: 323103-001
The NTB port supports the Type 0 configuration header. The first 10 DW of the Type 0
configuration header is shown in Table 78. The NTB sets the following parameters in the
configuration header.
• The class code field is defined per PCI Specification Revision 3.0 and is set to
0x068000 as shown in Table 79.
Figure 52. Intel
®
Xeon
®
Processor C5500/C3500 Series NTB Port - Nomenclature
Core Complex
PCIE
Root Port
(RP)
PCIE
Non_Transparent
Bridge (NTB)
Intel® Xeon® Processor C5500/C3500 Series
PCIE RCiEP
Local Host
PCIE EP
Table 78. Type 0 Configuration Header for Local and Remote Interface
Byte3 Byte2 Byte1 Byte0 DW
Device ID Vendor Id 00
Status Register Command Register 01
Class code Revision ID 02
BIST Header Type Latency Timer Cache Line Size 03
Base Address 0 04
Base Address 1 05
Base Address 2 06
Base Address 3 07
BAse Address 4 08
Base Address 5 09