Datasheet

Intel
®
Xeon
®
Processor C5500/C3500 Series
February 2010 Datasheet, Volume 1
Order Number: 323103-001 143
PCI Express Non-Transparent Bridge
3.6 Architecture Overview
The NTB provides two interfaces and sets of configuration registers, one for each of the
interfaces shown in Figure 52. The interface to the on-chip CPU complex is referred to
as the local host interface. The external interface is referred to as the remote host
interface. The NTB local host interface appears as a Root Complex Integrated Endpoint
(RCiEP) to the local host and the NTB’s remote interface appears as a PCI Express
Endpoint to the remote host. Both sides expose Type 0 configuration header to
discovery software, to both the local host and the remote host interface.
The NTB port supports the following sets of registers
• Type 0 configuration space registers with BAR definition on each side of the NTB.
• PCIE Capability Structure Configuration Registers registers with device capabilities.
• PCIE Capability Structure Configuration Registers registers with Device ID, Class
Code and interface configuration with link layer attributes such as port width, max
payload size etc.
• Configuration Shadowing – A set of registers present on each side of the NTB.
Secondary side registers are visible to primary side. Primary side registers are not
visible to the secondary side.
• Access Enable – A register is provided to enable blocking configuration register
access from the secondary side of the NTB. See bit 0 in Section 3.21.1.12,
“NTBCNTL: NTB Control” .
• Limit Registers– Limit registers can be used to limit the size of a memory window to
less than the size specified in the PCI BAR. PCI BAR sizes are always a power of 2,
e.g. 4GB, 8GB, 16GB. The limit registers allow the user to select any value to a 4KB
resolution within any window defined by the PCI BAR. For example if the PCI BAR
defines 8GB region the limit register could be used to limit that region to 6GB.
• Scratchpad – A set of 16, 32b registers used for inter-processor communication.
These registers can be seen from both sides of the NTB.
• Doorbell – Two 16-bit doorbell registers (PDOORBELL and SDOORBELL) enabling
each side of the NTB to interrupt the opposite side. There is one set on the primary
side PDOORBELL and one set on the secondary side SDOORBELL.
• Semaphore – This is a single register that can be seen from both sides of the NTB.
The semaphore register allows SW a mechanism of controlling write access into
scratchpad. This semaphore has a “read 0 to set”, “write 1 to clear” attribute and is
visible from both sides of the NTB. This register is used for NTB/RP configuration.
• B2B Scratchpad – A set of 16, 32b registers used for inter-processor
communication between two NTBs.
• B2B Doorbell – A 16-bit doorbell register (B2BDOORBELL) enabling interrupt
passing between two NTBs.