Datasheet

PCI Express Non-Transparent Bridge
Intel
®
Xeon
®
Processor C5500/C3500 Series
Datasheet, Volume 1 February 2010
136 Order Number: 323103-001
• Supports peer-to-peer transactions upstream and downstream across NTB.
Capabilities for NTB are the same as defined for PCIE ports. See Section 3.7, “NTB
Inbound Transactions” and Section 3.8, “Outbound Transactions” for details.
• Supports sixteen, 32-bit scratch pad registers, (total 64B) that are accessible
through the BAR0 configuration space.
• Supports two, 16-bit doorbell registers (PDOORBELL and SDOORBELL) that are
accessible through the BAR0 configuration space.
• Supports INTx, MSI and MSI-X mechanism for interrupts on both sides of the NTB
in the upstream direction only.
— For example a write to the PDOORBELL from the link partner attached to the
secondary side of the NTB will result in a INTx, MSI or MSI-X in the upstream
direction to the local Intel
®
Xeon
®
processor C5500/C3500 series.
— A write from the local host on the Intel
®
Xeon
®
processor C5500/C3500 series
to the SDOORBELL will result in a INTx, MSI or MSI-X in the upstream direction
to the link partner connected to the secondary side of the NTB.
• Capability for passing doorbell/scratchpad across back-to-back NTB configuration.
3.2.1 Features Not Supported on the Intel
®
Xeon
®
Processor C5500/
C3500 Series NTB
• NTB does not support x16 link configuration
• NTB does not support IO space BARs
• NTB does not support vendor defined PCIE message transactions. These messages
are silently dropped if received.
3.3 Non-Transparent Bridge vs. Transparent Bridge
A PCIE TB provides electrical isolation and enables design expansion for the host I/O
subsystem. The host processor enumerates the entire system through discovery of TBs
and Endpoint devices. The presence of a TB between the host and an Endpoint device is
transparent to the device and the device driver associated with that device. The Intel
®
Xeon
®
processor C5500/C3500 series TB does not require a device driver of its own as
it does not have any resources that must be managed by software during run time. The
TB exposes Control and Status Register with Type 1 header, informing the host
processor to continue enumeration beyond the bridge until it discovers Endpoint
devices downstream from the bridge. The Endpoint devices will support Configuration
Registers with Type 0 header and terminate the enumeration process. Figure 46 shows
a system with TBs and Endpoint devices.