Datasheet

Intel
®
Xeon
®
Processor C5500/C3500 Series
February 2010 Datasheet, Volume 1
Order Number: 323103-001 135
PCI Express Non-Transparent Bridge
3.0 PCI Express Non-Transparent Bridge
3.1 Introduction
PCI Express* non-transparent bridge (NTB) acts as a gateway that enables high
performance, low overhead communication between two intelligent subsystems, the
local and the remote subsystems. The NTB allows a local processor to independently
configure and control the local subsystem, provides isolation of the local host memory
domain from the remote host memory domain while enabling status and data exchange
between the two domains.
When used in conjunction with Intel
®
VT-d2 both primary and secondary addresses are
guest addresses. When Intel
®
VT-d2 is not used the secondary side of the bridge is a
guest address and the primary side of the bridge is a physical address.
3.2 NTB Features Supported on Intel
®
Xeon
®
Processor
C5500/C3500 Series
The Intel
®
Xeon
®
processor C5500/C3500 series supports the following NTB features.
Details are specified in the subsequent sections of this document.
• PCIE Port 0 can be configured to be either a transparent bridge (TB) or an NTB.
— NTB link width can support x4 or x8
• The NTB port supports Gen1 and Gen2 speed.
• The NTB supports two usage models
— NTB attached to a Root Port (RP)
— NTB attached to another NTB
• Supports 3 64b BARs
— BAR 0/1 for configuration space
— BAR 2/3 and BAR 4/5 are prefetchable memory windows that can access both
32b and 64b address space through 64 bit BARs.
— BAR 2/3 and 4/5 support direct address translation
— BAR 2/3 and 4/5 support limit registers
• Limit registers can be used to limit the size of a memory window to less
than the size specified in the PCI BAR. PCI BAR sizes are always a power
of 2, e.g. 4GB, 8GB, 16GB. The limit registers allow the user to select any
value to a 4KB resolution within any window defined by the PCI BAR. For
example if the PCI BAR defines 8GB region the limit register could be
used to limit that region to 6GB.
• One use case for limit registers also provide a mechanism to allow
separation of code space from data space.
• Supports posted writes and non-posted memory read transactions across NTB.