Datasheet

Interfaces
Intel
®
Xeon
®
Processor C5500/C3500 Series
Datasheet, Volume 1 February 2010
134 Order Number: 323103-001
2.7 Direct Media Interface (DMI2)
The Direct Media Interface in the IIO is responsible for sending and receiving packets/
commands to the PCH. The DMI is an extension of the standard PCI Express
specification with special commands/features added to mimic the legacy Hub Interface.
DMI2 is the second generation extension of DMI. See the DMI Specification, Revision
2.0, for more DMI2 details.
Note: Other references to DMI are referring to the same DMI2-compliant interface described
above.
DMI connects the processor and the PCH chip-to-chip. DMI2 is supported. The DMI is
similar to a four-lane PCI Express interface supporting up to 1 GB/s of bandwidth in
each direction. Only DMI x4 configuration is supported.
In DP configurations, the DMI port of the non-legacy processor may be configured as a
a single PCIe port, supporting PCIe Gen1 only.
2.7.1 DMI Error Flow
DMI can only generate SERR in response to errors, never SCI, SMI, MSI, PCI INT, or
GPE. Any DMI related SERR activity is associated with Device 0.
2.7.2 Processor/PCH Compatibility Assumptions
The Intel
®
Xeon
®
processor C5500/C3500 series is compatible with the PCH and is not
compatible with any previous (G)MCH or ICH products.
2.7.3 DMI Link Down
The DMI link going down is a fatal, unrecoverable error. If the DMI data link goes to
data link down, after the link was up, then the DMI link hangs the system by not
allowing the link to retrain to prevent data corruption. This is controlled by the PCH.
Downstream transactions that had been successfully transmitted across the link prior
to the link going down may be processed as normal. No completions from downstream,
non-posted transactions are returned upstream over the DMI link after a link down
event.
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