Datasheet

Interfaces
Intel
®
Xeon
®
Processor C5500/C3500 Series
Datasheet, Volume 1 February 2010
130 Order Number: 323103-001
2.6.14.3 Completions for Locked Read Requests
LkRdCmp and RdCmp are aliased -i.e. either of these completion types can terminate a
locked/non-locked read request.
2.6.15 PCI Express RAS
The PCI Express Advanced Error Reporting (AER) capability is supported. See the PCI
Express Base Specification, Revision 2.0 for details.
2.6.16 ECRC Support
ECRC is not supported. ECRC is ignored and dropped on all incoming packets and is not
generated on any outgoing packet.
2.6.17 Completion Timeout
For all non-posted requests issued on PCI Express/DMI, a timer is maintained that
tracks the max completion time for that request.
The OS selects a coarse range for the timeout value. The timeout value is
programmable from 10 ms all the way up to 64s. See the DEVCAP2: PCI Express
Device Capabilities register for additional control that provides for the 17s to 64s
timeout range.
See Section 11.0, “Reliability, Availability, Serviceability (RAS)” for details of responses
returned by IIO to various interfaces on a completion timeout event. AER-required
error logging and escalation happen as well. In addition to the AER error logging, IIO
also sets the locked read timeout bit in “MISCCTRLSTS: Misc Control and Status
Registers”, if the completion timeout happened on a locked read request.
2.6.18 Data Poisoning
The IIO supports forwarding poisoned information between Intel
®
QPI and PCI Express
and vice-versa. The IIO also supports forwarding poisoned data between peer PCI
Express ports.
The IIO has a mode in which poisoned data is never sent out on PCI Express i.e. any
packet with poisoned data is dropped internally in the IIO and an error escalation done.
2.6.19 Role-Based Error Reporting
The role-based error reporting that is specified in the PCI Express Base Specification,
Revision 2.0 spec is supported.
A Poisoned TLP that IIO receives on peer-to-peer packets is treated as an advisory non-
fatal error condition i.e. ERR_COR signaled and poisoned information propagated peer-
to-peer. Poisoned TLP that is received on packets that are destined towards DRAM
memory or poisoned TLP packets that target the interrupt address range, are
forwarded to the coherent interface with the poison bit set, provided the coherent
interface is enabled to set the poisoned bit via QPIPC[12] bit. In such a case the
received poisoned TLP condition is treated as advisory non-fatal error on the PCI
Express interface. If that bit is not set, then the received poisoned TLP condition is
treated as a normal non-fatal error. The packet would be dropped if it is a posted
transaction. A “master abort” response is sent on the coherent interface if a poisoned
TLP is received for an outstanding non-posted request.