Datasheet
Intel
®
Xeon
®
Processor C5500/C3500 Series
February 2010 Datasheet, Volume 1
Order Number: 323103-001 13
7.4 Virtual Legacy Wires (VLW) .............................................................................. 346
7.5 Platform Interrupts.......................................................................................... 347
7.6 Interrupt Flow................................................................................................. 347
7.6.1 Legacy Interrupt Handled By IIO Module IOxAPIC..................................... 348
7.6.2 MSI Interrupt ...................................................................................... 348
8.0 Power Management............................................................................................... 349
8.1 Introduction ................................................................................................... 349
8.1.1 ACPI States Supported.......................................................................... 349
8.1.2 Supported System Power States............................................................. 350
8.1.3 Processor Core/Package States .............................................................. 351
8.1.4 Integrated Memory Controller States ...................................................... 351
8.1.5 PCIe Link States................................................................................... 351
8.1.6 DMI States.......................................................................................... 352
8.1.7 Intel
®
QPI States................................................................................. 352
8.1.8 Intel
®
QuickData Technology State......................................................... 352
8.1.9 Interface State Combinations................................................................. 352
8.1.10 Supported DMI Power States ................................................................. 353
8.2 Processor Core Power Management.................................................................... 353
8.2.1 Enhanced Intel SpeedStep
®
Technology.................................................. 353
8.2.2 Low-Power Idle States .......................................................................... 354
8.2.3 Requesting Low-Power Idle States.......................................................... 355
8.2.4 Core C-States...................................................................................... 356
8.2.4.1 Core C0 State....................................................................... 356
8.2.4.2 Core C1E State..................................................................... 356
8.2.4.3 Core C3 State....................................................................... 357
8.2.4.4 Core C6 State....................................................................... 357
8.2.4.5 C-State Auto-Demotion.......................................................... 357
8.2.5 Package C-States................................................................................. 357
8.2.5.1 Package C0.......................................................................... 359
8.2.5.2 Package C1E ........................................................................ 359
8.2.5.3 Package C3 State.................................................................. 359
8.2.5.4 Package C6 State.................................................................. 360
8.3 IMC Power Management................................................................................... 360
8.3.1 Disabling Unused System Memory Outputs .............................................. 360
8.3.2 DRAM Power Management and Initialization............................................. 360
8.3.2.1 Initialization Role of CKE........................................................ 360
8.3.2.2 Conditional Self-Refresh......................................................... 360
8.3.2.3 Dynamic Power Down Operation ............................................. 361
8.3.2.4 DRAM I/O Power Management................................................ 361
8.3.2.5 Asynch DRAM Self Refresh (ADR)............................................ 361
8.4 Device and Slot Power Limits ............................................................................ 365
8.4.1 DMI Power Management Rules for the IIO Module..................................... 365
8.4.2 Support for P-States............................................................................. 365
8.4.3 S0 -> S1 Transition.............................................................................. 365
8.4.4 S1 -> S0 Transition.............................................................................. 366
8.4.5 S0 -> S3/S4/S5 Transition .................................................................... 366
8.5 PCIe Power Management.................................................................................. 367
8.5.1 Power Management Messages................................................................ 367
8.6 DMI Power Management................................................................................... 367
8.7 Intel
®
QPI Power Management.......................................................................... 368
8.8 Intel
®
QuickData Technology Power Management................................................ 368
8.8.1 Power Management w/Assistance from OS-Level Software......................... 368
9.0 Thermal Management............................................................................................ 369
10.0 Reset..................................................................................................................... 370