Datasheet

Interfaces
Intel
®
Xeon
®
Processor C5500/C3500 Series
Datasheet, Volume 1 February 2010
128 Order Number: 323103-001
2.6.12 Transaction Descriptor
The PCI Express Base Specification, Revision 2.0 defines a field in the header called the
Transaction Descriptor. This descriptor comprises three sub-fields:
•Transaction ID
Attributes
Traffic class
2.6.12.1 Transaction ID
The Transaction ID uniquely identifies every transaction in the system. The Transaction
ID comprises four sub-fields described in Table 73. This table provides details on how
this field in the Express header is populated by IIO.
Table 73. PCI Express Transaction ID Handling
Field Definition IIO as Requester
IIO as
Completer
Bus
Number
Specifies the bus number that the requester
resides on.
The IIO fills this field with the internal Bus
Number that the PCI Express cluster resides
on.
The IIO preserves
this field from the
request and
copies it into the
completion.
Device
Number
Specifies the device number of the requester.
NOTE: Normally, The 5-bit Device ID is
required to be zero in the RID that consists of
BDF, but when ARI is enabled, the 8-bit DF is
now interpreted as an 8-bit Function Number
with the Device Number equal to zero
implied.
For CPU requests, the IIO fills this field with
the Device Number that the PCI Express
cluster owns. For DMA requests, the IIO fills
this field with the device number of the DMA
engine (Device#10)
Function
Number
Specifies the function number of the
requester.
The IIO fills this field in with its Function
Number that the PCI Express cluster owns
(zero).
Tag
Identifies a unique identifier for every
transaction that requires a completion. Since
the PCI Express ordering rules allow read
requests to pass other read requests, this
field is used to reorder separate completions
if they return from the target out-of-order.
NP tx: The IIO fills this field in with a value
such that every pending request carries a
unique Tag.
NP Tag[7:5]=Intel
®
QPI Source NodeID[4:2].
Bits 7:5 can be non-zero only when 8-bit tag
usage is enabled. Otherwise, IIO always zeros
out 7:5.
NP Tag[4:0]=Any algorithm that guarantees
uniqueness across all pending NP requests
from the port.
P Tx: No uniqueness guaranteed.
Tag[7:0]=Intel
®
QPI Source NodeID[7:0] for
CPU requests. Bits 7:5 can be non-zero only
when 8-bit tag usage is enabled. Otherwise,
IIO always zeros out 7:5.