Datasheet

Intel
®
Xeon
®
Processor C5500/C3500 Series
February 2010 Datasheet, Volume 1
Order Number: 323103-001 127
Interfaces
2.6.10 Outbound Messages Supported
Table 72 provides a list of all the messages supported as an initiator on a PCI Express
port (DMI messages are not included in this table).
2.6.10.1 Unlock
This message is transmitted by IIO at the end of a lock sequence. This message is
transmitted irrespective of whether PCI Express lock was established or not and also
regardless of whether the lock sequence terminated in an error or not.
2.6.10.2 EOI
EOI messages will be broadcast from the coherent interface to all the PCI Express
interfaces/DMI ports that have an APIC below them. Presence of an APIC is indicated
by the EOI enable bit in the MISCCTRLSTS: Misc Control and Status Register. This
ensures that the appropriate interrupt controller receives the end-of-interrupt.
The IIO has the capability to NOT broadcast/multicast EOI message to any of the PCI
Express/DMI ports and this is controlled via bit 0 in the EOI_CTRL register. When this
bit is set, IIO simply drops the EOI message received from Intel
®
QPI and not send it
to any south agent. But IIO does send a normal compare for the message on Intel
®
QPI.
2.6.11 32/64 bit Addressing
For inbound and outbound memory reads and writes, the IIO supports the 64-bit
address format. If an outbound transaction’s address is less than 4 GB, then the IIO
will issue the transaction with a 32-bit addressing format on PCI Express. Only when
the address is greater than 4 GB then IIO will initiate transaction with 64-bit
addressing format.
Table 72. Outgoing PCI Express Message Cycles
PCI Express
Transaction
Address Space or
Message
Reason for Issue
Outbound Messages
Unlock
Releases a locked read or write transaction previously issued on PCI
Express.
PME_Turn_Off
When PME_TO bit is set, send this message to the associated PCI
Express port.
PM_REQUEST_ACK
(DLLP)
Acknowledges that the IIO received a PM_ENTER_L1 message. This
message is continuously issued until the receiver link is idle. See the PCI
Express Base Specification, Revision 2.0 for details.
PM_Active_State_Nak When IIO receives a PM_Active_State_Request_L1.
Set_Slot_Power_Limit
Message that is sent to PCI Express device when software wrote to the
Slot Capabilities Register or the PCI Express link transitions to DL_Up
state. See PCI Express Base Specification, Revision 2.0 for more
details.
ATC Translation Invalidate
When a translation is changed in the TA and that translation might be
contained within an ATC in an endpoint, the host system must send an
invalidation to the ATC via IIO to maintain proper synchronization
between the translation tables and the translation caches.
Intel Chipset-specifc
Vendor-defined
EOI
End-of-interrupt cycle received on Intel
®
QPI. IIO broadcasts this
message to all downstream PCI Express and DMI ports that have an I/
OxAPIC below them.