Datasheet

Interfaces
Intel
®
Xeon
®
Processor C5500/C3500 Series
Datasheet, Volume 1 February 2010
126 Order Number: 323103-001
2.6.8 Outbound Transactions
This section describes the IIO behavior towards outbound transactions. Throughout the
rest of the section, outbound refers to the direction from processor towards I/O.
2.6.8.1 Memory, I/O and Configuration Transactions Supported
Table 71 lists the possible outbound memory, I/O and configuration transactions.
2.6.9 Lock Support
For legacy PCI functionality, bus locks are supported through an explicit sequence of
events. Intel
®
Xeon
®
processor C5500/C3500 series can receive a locked transaction
sequence on the Intel
®
QuickPath Interconnect interface directed to a PCI Express
port.
Table 71. Outgoing PCI Express Memory, I/O and Configuration Request/Completion
Cycles
PCI Express
Transaction
Address Space or
Message
Reason for Issue
Outbound Write Requests
Memory
Memory-mapped I/O write targeting PCI Express
device.
I/O Legacy I/O write targeting PCI Express legacy device
Configuration Configuration write targeting PCI Express device.
Outbound Completions
for Inbound Write
Requests
I/O Unsupported. Transaction will be returned as UR.
Configuration
(Type0 or Type1)
Unsupported. Transaction will be returned as UR.
Outbound Read Requests
Memory
Memory-mapped I/O read targeting PCI Express
device.
I/O legacy I/O read targeting PCI Express device.
Configuration Configuration read targeting PCI Express device.
Outbound Completions
for Inbound Read
Requests
Memory
Response for an inbound read to main memory or a
peer I/O device.
I/O Unsupported. Transaction will be returned as UR.
Configuration
(Type0 or Type1)
Unsupported. Transaction will be returned as UR.