Datasheet

Interfaces
Intel
®
Xeon
®
Processor C5500/C3500 Series
Datasheet, Volume 1 February 2010
124 Order Number: 323103-001
2.6.5.2 ASSERT_GPE / DEASSERT_GPE
General Purpose Event (GPE) consists of two messages: Assert_GPE and
Deassert_GPE. Upon receipt of a Assert_GPE message from a PCI Express port, the IIO
forwards the message to the PCH. When the GPE event has been serviced, the IIO will
receive a Deassert_GPE message on the PCI Express port. At this point the IIO can
send the deassert_GPE message on DMI.
2.6.6 Configuration Retry Completions
When a PCI Express port receives a configuration completion packet with a
configuration retry status, it reissues the transaction on the affected PCI Express port
or completes it. The PCI Express Base Specification, Revision 2.0 spec allows for
Configuration retry from PCI Express to be visible to software by returning a value of
0x01 on configuration retry (CRS status) on configuration reads to the VendorID
register.
The following is a summary of when a configuration request will be re-issued:
• When configuration retry software visibility is disabled via the root control register
— A configuration request (read or write and regardless of address) is reissued
when a CRS response is received for the request and the Configuration Retry
Timeout timer has not expired. The Configuration Retry Timeout timer is set via
the “CTOCTRL: Completion Timeout Control” register. If the timer has expired,
a CRS response received after that will be aborted and a UR response is sent.
— An “Timeout Abort” response is sent on the coherent interface (except in the
DP profile) at the expiry of every 48 ms from the time the request has been
first sent on PCI Express till the request has been retired.
• When configuration retry software visibility is enabled via the root control register.
— The reissue rules as stated previously apply to all configuration transactions,
except for configuration reads to vendor ID field at DWORD offset 0x0. When a
CRS response is received on a configuration read to VendorID field at word
address 0x0, IIO completes the transaction normally with a value of 0x01 in
the data field and all 1s in any other bytes included in the read. See the PCI
Express Base Specification, Revision 2.0 for more details.
An Intel
®
Xeon
®
processor C5500/C3500 series-aborted configuration transaction is
treated as if the transaction returned a UR status on PCI Express except that the
associated PCI header space status and the AER status/log registers are not set.