Datasheet

Intel
®
Xeon
®
Processor C5500/C3500 Series
February 2010 Datasheet, Volume 1
Order Number: 323103-001 123
Interfaces
Entry into or exit from degraded mode are reported to software in the MISCCTRLSTS
register, and also records which lane failed. Software can then report the flaky
hardware behavior to the system operator for attention, by generating a system
interrupt.
2.6.2.5 Lane Reversal
Lane reversal is supported on all PCI Express ports, regardless of the link width i.e.
lane reversal works in x16, x8, and x4 link widths. See Table 69 for lane reversal
combinations supported. A x2 card can be plugged into a x16, x8, or x4 slot and work
as x2 only if lane-reversal is not done, otherwise it would operate in x1 mode.
2.6.3 Gen1/Gen2 Speed Selection
In general, Gen1 vs. Gen2 speed will be negotiated per the inband mechanism defined
in the Gen2 PCI Express Specification. In addition, Gen2 speed can be prevented from
negotiating if PE_GEN2_DISABLE# strap is set to 1 at reset deassertion. This strap
controls all ports together. In addition the ‘Target Link Speed’ field in LNKCON2 register
can be used by software to force a certain speed on the link.
2.6.4 Link Upconfigure Capability
Upconfigure is an optional PCI Express Base Specification, Revision 2.0 feature that
allows the SW to increase or decrease the link width. Possible uses are for bandwidth
matching and power savings.
The IIO supports link upconfigure capability. The IIO sends "1" during link training in
Configuration state, in bit 6 of symbol 4 of a TS2 to indicate this capability when the
upcfgcpable bit is set.
2.6.5 Error Reporting
PCI Express reports many error conditions through explicit error messages: ERR_COR,
ERR_NONFATAL, ERR_FATAL. One of the following can be programmed when one of
these error messages is received: (See “PCICMD: PCI Command” and “MSIXMSGCTL:
MSI-X Messae Control” registers).
Generate MSI
Forward the messages to PCH
See the PCI Express Base Specification, Revision 2.0 for details of the standard status
bits that are set when a root complex receives one of these messages.
2.6.5.1 Chipset-Specific Vendor-Defined
These vendor-defined messages are identified with a Vendor ID of 8086 in the message
header and a specific message code. See the Direct Media Interface Specification Rev
1.0 for details.
x4
x2 on either lanes 1-0, 0-1
x1 on either lanes 0, 1, 2, 3
x2 x1 on either lanes 0, 1
1. This is the native width the link is running at when degraded mode operation kicks-in
Table 69. Supported Degraded Modes in IIO
Original Link Width
1
Degraded Mode Link Width and Lanes Numbers