Datasheet
Interfaces
Intel
®
Xeon
®
Processor C5500/C3500 Series
Datasheet, Volume 1 February 2010
122 Order Number: 323103-001
The bifurcation control registers are sticky and BIOS can choose to program the
register and cause an IIO reset and the appropriate bifurcation will take effect on exit
from that reset.
2.6.2.4 Degraded Mode
Degraded mode is supported for x16, x8, and x4 link widths. Intel
®
Xeon
®
processor
C5500/C3500 series supports degraded mode operation at half the original width, a
quarter and an eighth of the original width or a x1. The IIO supported degradation
modes are limited to the outer lanes only (including lane reversal). Lane degradation
remapping should occur in the physical layer and the link and transaction layers are
transparent to the link width change. The degraded mode widths are automatically
attempted every time the PCI Express link is trained. The events that trigger the PCI
Express link training are per the PCI Express Base Specification, Revision 2.0 . For
example, if a packet is retried on the link N times (where N is per the PCI Express Base
Specification, Revision 2.0 ) then a physical layer retraining is automatically initiated.
When this retraining happens, the IIO attempts to negotiate at the link width that it is
currnetly operating at and if that fails, the IIO attempts to negotiate a lower link width
per the degraded mode operation.
Degraded modes are shown in Table 69 are supported. A higher width degraded mode
will be attempted before trying any lower width degraded modes.
Table 68. Link Width Strapping Options
PECFGSEL[2:0] Behavior of PCIe Port
000 Reserved
001 Reserved
010
x4x4x8:
Dev6(x4, lanes 15-12), Dev5(x4, lanes 11-8), Dev3(x8, lanes 7-0)
011
x8x4x4:
Dev5(x8, lanes 15-8), Dev4(x4, lanes 7-4), Dev3(x4, lanes 3-0)
100
Wait-On-BIOS:
optional when all RPs, must use if using NTB
101
x4x4x4x4:
Dev6(x4, lanes 15-12), Dev5(x4, lanes 11-8), Dev4(x4, lanes 7-4),
Dev3(x4, lanes 3-0)
110
x8x8:
Dev5(x8, lanes 15-8), Dev3(x8, lanes 7-0)
111
x16:
Dev3(x16, lanes 15-0)
Table 69. Supported Degraded Modes in IIO
Original Link Width
1
Degraded Mode Link Width and Lanes Numbers
x16
x8 on either lanes 7-0, 0-7, 15-8, 8-15
x4 on either lanes 3-0, 0-3,4-7, 7-4, 8-11, 11-8, 12-15, 15-12
x2 on either lanes 1-0, 0-1,4-5, 5-4, 8-9, 9-8, 12-13, 13-12
x1 on either lanes 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15
x8
x4 on either lanes 7-4, 4-7, 3-0, 0-3
x2 on either lanes 5-4, 4-5, 1-0, 0-1
x1 on either lanes 0, 1, 2, 3, 4, 5, 6, 7