Datasheet

Intel
®
Xeon
®
Processor C5500/C3500 Series
February 2010 Datasheet, Volume 1
Order Number: 323103-001 121
Interfaces
During link training, the processor will attempt link negotiation starting from the
highest defined link width and ramp down to the nearest supported link width that
passes negotiation. For example, when x16 support is defined the port will first attempt
negotiation as a single x16. If that fails, an attempt is made to negotiate as a single x8
link. If that fails an attempt is made to negotiate as a single x4 link. If that fails an
attempt is made to negotiate as a single x2 link and finally if that fails it will attempt to
train as a single x1 link.
Each of the widths (x16, x8, x4) are trained in both the non-lane-reversed and lane-
reversed modes. Widths of (x2 and x1) are considered degraded special cases of a x4
port and have limited lane reversal as defined in Section 2.6.2.5, “Lane Reversal” . For
example, x16 link width is trained in both the non-lane-reversed and lane-reversed
modes before training for a single x8 configuration is attempted by the IIO. A x1 link is
the minimum required link width that must be supported per the PCI Express Base
Specification, Revision 2.0.
2.6.2.2 Port Bifurcation
IIO port bifurcation support is available via different means:
• Using the hardware strap pins (PECFGSEL[2:0]) as shown in Table 68.
• Via BIOS by appropriately programming the PCIE_PRT0_BIF_CTL register.
2.6.2.3 Port Bifurcation via BIOS
When the BIOS needs to control port bifurcation, the hardware strap needs to be set to
“Wait_on_BIOS”. This instructs the LTSSM to not train until the BIOS explicitly enables
port bifurcation by programming the PCIE_IOU0_BIF_CTRL register. The default of the
latter register is such as to halt the LTSSM from training at poweron, provided the strap
is set to “Wait_on_BIOS”. When the BIOS programs the appropriate bifurcation
information into the register, it can initiate port bifurcation by writing to the “Start
bifurcation” bit in the register. Once BIOS has started the port bifurcation, it cannot
initiate any more bifurcation commands without resetting the IIO. Software can initiate
link retraining within a sub-port or even change the width of a sub-port (by
programming the PCIE_PRT/DMI_LANE_MSK register) any number of times without
resetting the IIO.
The following is pseudo-code for how the register and strap work together to control
port bifurcation. “Strap to ltssm” indicates the IIO internal strap to the Link Training
and Status State Machine (LTSSM).
If (PCIE_IOU0_BIF_CTRL[2:0] == 111)
If (<PECFGSEL[2:0]>!= 100 ) {
Strap to ltssm = strap
} else {
Wait for “PCIE_IOU0_BIF_CTRL[3]” bit to be set
Strap to ltssm = csr
}
} else {
Strap to ltssm = csr
}