Datasheet
Intel
®
Xeon
®
Processor C5500/C3500 Series
Datasheet, Volume 1 February 2010
12 Order Number: 323103-001
5.6 Configuration Register Ordering Rules ................................................................319
5.7 Intel
®
VT-d Ordering Exceptions........................................................................319
6.0 System Address Map..............................................................................................320
6.1 Memory Address Space ....................................................................................321
6.1.1 System DRAM Memory Regions ..............................................................322
6.1.2 VGA/SMM and Legacy C/D/E/F Regions....................................................322
6.1.2.1 VGA/SMM Memory Space .......................................................323
6.1.2.2 C/D/E/F Segments.................................................................323
6.1.3 Address Region Between 1 MB and TOLM.................................................324
6.1.3.1 Relocatable TSeg...................................................................324
6.1.4 PAM Memory Area Details ......................................................................324
6.1.5 ISA Hole (15 MB –16 MB) ......................................................................324
6.1.6 Memory Address Range TOLM – 4 GB......................................................325
6.1.6.1 PCI Express Memory Mapped Configuration Space (PCI MMCFG)..325
6.1.6.2 MMIOL.................................................................................325
6.1.6.3 I/OxAPIC Memory Space ........................................................325
6.1.6.4 HPET/Others.........................................................................326
6.1.6.5 Local XAPIC..........................................................................326
6.1.6.6 Firmware..............................................................................326
6.1.7 Address Regions above 4 GB..................................................................327
6.1.7.1 High System Memory.............................................................327
6.1.7.2 Memory Mapped IO High ........................................................327
6.1.8 Protected System DRAM Regions ............................................................327
6.2 IO Address Space ............................................................................................328
6.2.1 VGA I/O Addresses ...............................................................................328
6.2.2 ISA Addresses......................................................................................328
6.2.3 CFC/CF8 Addresses...............................................................................328
6.2.4 PCIe Device I/O Addresses.....................................................................328
6.3 IIO Address Map Notes.....................................................................................329
6.3.1 Memory Recovery.................................................................................329
6.3.2 Non-Coherent Address Space .................................................................329
6.4 IIO Address Decoding.......................................................................................329
6.4.1 Outbound Address Decoding...................................................................329
6.4.1.1 General Overview..................................................................329
6.4.1.2 FWH Decoding ......................................................................331
6.4.1.3 I/OxAPIC Decoding................................................................331
6.4.1.4 Other Outbound Target Decoding.............................................331
6.4.1.5 Summary of Outbound Target Decoder Entries ..........................331
6.4.1.6 Summary of Outbound Memory/IO/Configuration Decoding.........333
6.4.2 Inbound Address Decoding.....................................................................335
6.4.2.1 Overview..............................................................................335
6.4.2.2 Summary of Inbound Address Decoding ...................................337
6.4.3 Intel
®
VT-d Address Map Implications .....................................................338
7.0 Interrupts..............................................................................................................339
7.1 Overview........................................................................................................339
7.2 Legacy PCI Interrupt Handling...........................................................................339
7.2.1 Integrated I/OxAPIC .............................................................................340
7.2.1.1 Integrated I/OxAPIC EOI Flow.................................................341
7.2.2 PCI Express INTx Message Ordering........................................................341
7.2.3 INTR_Ack/INTR_Ack_Reply Messages......................................................342
7.3 MSI ...............................................................................................................342
7.3.1 Interrupt Remapping.............................................................................344
7.3.2 MSI Forwarding: IA32 Processor-based Platform.......................................345
7.3.2.1 Legacy Logical Mode Interrupts ...............................................345
7.3.3 External IOxAPIC Support......................................................................346