Datasheet

Intel
®
Xeon
®
Processor C5500/C3500 Series
February 2010 Datasheet, Volume 1
Order Number: 323103-001 119
Interfaces
2.6 PCI Express Interface
This section describes the PCI Express* interface capabilities of the processor. See the
latest PCI Express Base Specification, Revision 2.0 for PCI Express details.
The processor has four PCI Express controllers, allowing the sixteen lanes to be
controlled as a single x16 port, or two x8 ports, or one x8 port and two x4 ports, or
four x4 ports.
2.6.1 PCI Express Architecture
PCI Express configuration uses standard mechanisms as defined in the PCI Plug-and-
Play specification. The initial speed of 1.25 GHz results in 2.5 Gb/s per direction per
lane. All processor PCI Express ports can negotiate between 2.5 GT/s and 5.0 GT/s
speed per the inband mechanism defined in Gen2 PCI Express Specification. Note that
the PCI Express port muxed with DMI will only support negotiation to 2.5 GT/s.
The PCI Express architecture is specified in three layers: Transaction Layer, Data Link
Layer, and Physical Layer. The partitioning in the component is not necessarily along
these same boundaries. See Figure 44.
PCI Express uses packets to communicate information between components. Packets
are formed in the Transaction and Data Link Layers to carry the information from the
transmitting component to the receiving component. As the transmitted packets flow
through the other layers, they are extended with additional information necessary to
handle packets at those layers. At the receiving side the reverse process occurs and
packets get transformed from their Physical Layer representation to the Data Link
Layer representation and finally (for Transaction Layer Packets) to the form that can be
processed by the Transaction Layer of the receiving device.
Figure 44. PCI Express Layering Diagram