Datasheet

Interfaces
Intel
®
Xeon
®
Processor C5500/C3500 Series
Datasheet, Volume 1 February 2010
118 Order Number: 323103-001
2.5.12 Outgoing Request Buffer (ORB)
When an inbound request is issued onto Intel
®
QPI an ORB entry is allocated. This list
keeps all pertinent information about the transaction header needed to complete the
request. It also stores the cache line address for coherent transactions to allow conflict
checking with snoops (
used for conflict checking for other requests).
When a request is issued, a RTID (Requestor Transaction ID) is assigned based on
NodeID.
The ORB depth is 64 entries.
2.5.13 Time-Out Counter
Each entry in the ORB is tagged with a time-out value when it is allocated; the time-out
value is dependent on the transaction type. This separation allows for isolating a failing
transaction when dependence exists between transactions. Table 67 shows the four
time-out levels of transactions the IIO supports. Levels 2 and 6 are for transactions
that the IIO does not send. The levels should be programmed such that they are
increasing to allow the isolation of failing requests, and they should be programmed to
consistent values across all components in the system.
The ORB implements a single 8-bit time-out counter that increments at a
programmable rate. This rate is programmable via configuration registers to a timeout
between 2^8 cycles (IIO core) and 2^36 cycles. The time-out counter can also be
disabled.
For each supported level there is a configuration value that defines the number of
counter transitions for a given level before that transaction times-out. This value will be
referred to as the “level time-out”. It provides a range of possible time-out values
based on the counter speed and the “level time-out” in this configuration register.
Table 67 shows the possible values for each level at a given counter speed. The
configuration values should be programmed to increase as the level increases to
support longer time-out values for the higher levels.
The ORB time-out tag is assigned when the entry is allocated. The value is based on
current counter value + level time-out + 1. This tag supports an equal number of bits
to the counter (8-bits).
On each increment of the counter every ORB tag is checked to see if the value is equal
to the value of the counter. If a match is found on a valid transaction then it logged as
a time-out. A failed response status is then sent to the requesting south agent for non-
posted requests, and all Intel
®
QPI structures will be cleared of this request.
Table 67. Time-Out Level Classification for IIO
Level Request Type
1WbMtoI
2None
3
NcRd, NonSnpRd, NonSnpWr, RdCode,
InvWbMtoI, NcP2PB, IntPhysical, IntLogical, NcMsgS-
StartReq1, NcMsgB-StartReq2, PrefetchHint
4 NcWr, NcMsgB-VLW, NcMsgB-PmReq
5 NcMsgS-StopReq1, NcMsgS-StopReq2
6None