Datasheet
Intel
®
Xeon
®
Processor C5500/C3500 Series
February 2010 Datasheet, Volume 1
Order Number: 323103-001 117
Interfaces
2.5.11 Write Cache
The IIO write cache is used for pipelining of inbound coherent writes. This is done by
obtaining exclusive ownership of the cache line prior to ordering. Then writes are made
observable (M-state) in I/O order.
2.5.11.1 Write Cache Depth
The write cache size is 72 entries.
2.5.11.2 Coherent Write Flow
Inside the IIO, coherent writes follow a flow that starts with RFO (Request for
Ownership) followed by write a promotion to M-state.
IIO will issue an RFO command on Intel
®
QPI when it finds the write cache in I-state.
The “Invalidating Write” flow uses InvWbMtoI command. These requests return E-state
with no data. Once all the I/O ordering requirements have been met, the promotion
phase occurs and the state of the line becomes M.
In the case where a RFO hits an M-state line in the write cache, ownership is granted
immediately with no request appearing on Intel
®
QPI. This state will be referred to as
MG (M-state with RFO Granted). An RFO hitting E-state or MG-state in the write cache
indicates that another write has already received an RFO completion.
2.5.11.3 Eviction Policy
On reaching M-state the Write cache will evict the line immediately if no conflict is
found. If a subsequent RFO is pending in the conflict queue and it is the first RFO
conflict for this M-state line, then that write is given ownership. This is only allowed for
a single conflicting RFO, which restricts the write combining policy so that only 2 writes
may combine. This combining policy can be disabled with a configuration bit such that
each inbound write will result in a RFO-EWB flow on Intel
®
QPI.
Table 66. Profile Control
Feature Register Attribute
UP
Profile
DP
Profile
Notes
Source
Address
decoder
enable
QPIPCTRL RW disable enable
In UP profile all inbound requests are sent to a single
target NodeID.
Address bits QPIPMADDATA RW
<=40 bits
[39:0]
Can be reduced from the max to match a processor’s
support.
NodeID width QPIPCTRL RO 3-bit
Other NodeID bits will be set to zero, and will be
interpreted as zero when received.
Remote P2P <I/O SAD>
1
1. See Table 65 for details on which registers are affected.
RO disable
All IO Decoder entries (except LocalxAPIC) will be
disabled in DP Profile. See Table 65 for details.
Poison QPIPCTRL RW <prog> enable
When disabled any uncorrectable data error will be
treated identically to a header parity.
Snoop
Protocol
QPIPSB RW 0x0h 0x6h
2
2. This value needs to be programmed in both IIOs.
The snoop vector controls which agents the IIO
neeeds to broadcast snoops to.