Datasheet

Intel
®
Xeon
®
Processor C5500/C3500 Series
February 2010 Datasheet, Volume 1
Order Number: 323103-001 113
Interfaces
VNA and VN0 follow similar ordering to the message class being transported on it. With
Home message class requiring ordering across VNA/VN0 for the same cache line, all
other message classes have no ordering requirement.
2.5.3 Protocol Layer
The protocol layer is responsible for translating requests from the core into the Intel
®
QPI domain, and for maintaining protocol semantics. The IIO is a Intel
®
QPI caching
agent. It is also a fully-compliant ‘IO’ (home) agent for non-coherent I/O traffic. Source
Broadcast mode supports up to two peer caching agents. In DP, there are three peer
caching agents, but the other IIO is not snooped due to the invalidating write back
flow. Lock arbiter support in IA-32 systems is provided for up to eight processor lock
requesters.
The protocol layer supports 64 B cache lines. All transactions from PCI Express are
broken up into 64 B aligned requests to match Intel
®
QPI packet size and alignment
requirements. Transactions of less than a cache line are also supported using the 64 B
packet framework in Intel
®
QPI.
2.5.4 Snooping Modes
The IIO contains an 8b vector to indicate peer caching agents that specifies up to eight
peer agents that are involved in coherency. In UP profile this vector is always empty.
In DP system, there will be three peer caching agents: Home CPU, non-Home CPU, and
remote IIO. With the Invalidating Write Back flow, only both CPUs need to be snooped
so two bits are set. The IIO Intel
®
QPI logic handles the masking of snooping the home
agent.
2.5.5 IIO Source Address Decoder (SAD)
Every inbound request going to Intel
®
QPI must go through the source address
decoder to identify the home NodeID. For inbound requests, the home NodeID is the
target of the request. For remote peer to peer MMIO accesses, the inbound request
must also look at the SAD to determine the node ID of the other IIO. These are not
home NodeID requests.
In UP profile, all inbound requests are sent to a single target NodeID. When in this
mode the SAD is only used to decode legal ranges and the Target NodeID is ignored.
In DP profile the source address decoder is only used for decode of the DRAM address
ranges and APIC targets to find the correct home NodeID. In the DP profile the SAD
also decodes peer IIO address ranges. Other ranges including any protected memory
holes are decoded elsewhere. See Chapter 6.0, “System Address Map for more details.
The description of the source address decoder requires that some new terms be
defined:
Memory Address - Memory address range used for coherent and non-coherent
DRAM, MMIO, CSR.
Physical Address (PA) - This is the address field seen on Intel
®
QPI. (Differentiates
the virtual address seen on PCIe with Intel
®
VT-d and in the virtual address seen in
processor cores).
There are two basic spaces that use a source address decoder: Memory Address, and
PCI Express Bus Number. Each space is decoded separately. The space that is decoded
depends on the transaction type.