Datasheet

Intel
®
Xeon
®
Processor C5500/C3500 Series
February 2010 Datasheet, Volume 1
Order Number: 323103-001 111
Interfaces
2.4.9.5 Fault Handling
2.4.9.6 Reset/Initialization
2.4.9.7 Other Attributes
2.5 IIO Intel
®
QPI Coherent Interface and Address Decode
2.5.1 Introduction
This section discusses the internal coherent interface between the CPU complex and
the IIO complex. It is based on the Intel
®
QuickPath Interconnect. IIO address
decoding mechanisms are also discussed.
Table 60. Intel
®
QuickPath Interconnect Fault Handling Attributes
Interrupt Attribute Support
Machine check indication through Int No
Time-out hierarchy for fault diagnosis Only via 3-strike counter
Packet elimination for error isolation between partitions No
Abort time-out response Only via 3-strike counter
Table 61. Intel
®
QuickPath Interconnect Reset/Initialization Attributes
Interrupt Attribute Support
NodeID Assignment strap assignment
Processor accepting external configuration (NcRd, NcWr, CfgRd, CfgWr going to
CSRs) requests
Yes
Separation of reset domains between link and physical layer for link self-
healing
N/A
Separation of reset domains between routing/protocol and link layer for hot-
plug
N/A
Separation of reset domains between Intel
®
QuickPath Interconnect entities
and routing layer to allow sub-socket partitioning
No
Product specific fixed and configurable power on configuration values-
configurable through link parameter exchange.
Yes
Flexible firmware location through discovery during link initialization No
Packet routing during initialization before route table and address decoder is
initialized
Configurable through link
init parameter
Table 62. Intel
®
QuickPath Interconnect Other Attributes
General System Management Support
Protected system configuration region No
Support for various partitioning models No
Support for Link level power management Yes