Datasheet

Interfaces
Intel
®
Xeon
®
Processor C5500/C3500 Series
Datasheet, Volume 1 February 2010
110 Order Number: 323103-001
2.4.9.2 Intel
®
QuickPath Interconnect Coherent Protocol Attributes
2.4.9.3 Intel
®
QuickPath Interconnect Non-Coherent Protocol Attributes
2.4.9.4 Interrupt Handling
Table 57. Processor’s Intel
®
QuickPath Interconnect Coherent Protocol Attributes
Coherence Protocol Support
Supports Coherence protocol with in-order home channel Yes
Supports Coherence protocol with out-of-order home channel No
Supports Snoopy Caching agents Yes
Supports Directory Caching agents No
Supports Critical Chunk data order for coherent transactions Yes
Generates Buried HITM transaction cases No
Supports Receiving Buried HITM cases Yes
Table 58. Picket Post Platform Intel
®
QuickPath Interconnect Non-Coherent Protocol
Attributes
Non-Coherence Protocol Support
Peer-to-peer tunnel transactions Yes
Virtual Legacy Wire (VLW) transactions Yes
Special cycle transactions N/A
Locked accesses Yes
Table 59. Intel
®
QuickPath Interconnect Interrupts Attributes
Interrupt Attribute Support
Processor initiated Int Transaction on Intel
®
QuickPath Interconnect link Yes
Logical interrupts (IntLogical) Yes
Broadcast of logical and physical mode interrupts Yes
Logical Flat Addressing Mode (<= 8 threads) Yes
Logical Cluster Addressing Mode (<= 60 threads) Yes
EOI Yes
Support for INIT, NMI, SMI, and ExtINT through Virtual Legacy Wire (VLW) transaction Yes
Support for INIT, NMI, and ExtINT through Int transaction Yes
Limit on number of threads supported for inter-processor interrupts 8