Datasheet
Intel
®
Xeon
®
Processor C5500/C3500 Series
February 2010 Datasheet, Volume 1
Order Number: 323103-001 11
3.21.1.20 SPAD[0 - 15]: Scratchpad Registers 0 - 15............................... 293
3.21.1.21 SPADSEMA4: Scratchpad Semaphore....................................... 294
3.21.1.22 RSDBMSIXV70: Route Secondary Doorbell MSI-X Vector 7 to 0... 295
3.21.1.23 RSDBMSIXV158: Route Secondary Doorbell MSI-X Vector 15 to 8 296
3.21.1.24 WCCNTRL: Write Cache Control Register .................................. 297
3.21.1.25 B2BSPAD[0 - 15]: Back-to-back Scratchpad Registers 0 - 15...... 297
3.21.1.26 B2BDOORBELL: Back-to-Back Doorbell .................................... 298
3.21.1.27 B2BBAR0XLAT: Back-to-Back BAR 0/1 Translate ....................... 299
3.21.2 MSI-X MMIO Registers (NTB Primary side)............................................... 300
3.21.2.1 PMSIXTBL[0-3]: Primary MSI-X Table Address Register 0 - 3 ...... 301
3.21.2.2 PMSIXDATA[0-3]: Primary MSI-X Message Data Register 0 - 3.... 301
3.21.2.3 PMSIXVECCNTL[0-3]: Primary MSI-X Vector Control Register 0 -
3 .......................................................................................... 301
3.21.2.4 PMSIXPBA: Primary MSI-X Pending Bit Array Register................ 302
3.21.3 MSI-X MMIO registers (NTB Secondary Side) ........................................... 303
3.21.3.1 SMSIXTBL[0-3]: Secondary MSI-X Table Address Register 0 - 3 .. 304
3.21.3.2 SMSIXDATA[0-3]: Secondary MSI-X Message Data Register 0 - 3 304
3.21.3.3 SMSIXVECCNTL[0-3]: Secondary MSI-X Vector Control Register 0
- 3........................................................................................ 305
3.21.3.4 SMSIXPBA: Secondary MSI-X Pending Bit Array Register............ 305
4.0 Technologies ......................................................................................................... 306
4.1 Intel
®
Virtualization Technology (Intel
®
VT) ....................................................... 306
4.1.1 Intel
®
VT-x Objectives.......................................................................... 306
4.1.2 Intel
®
VT-x Features ............................................................................ 307
4.1.3 Intel
®
VT-d Objectives.......................................................................... 307
4.1.4 Intel
®
VT-d Features ............................................................................ 308
4.1.5 Intel
®
VT-d Features Not Supported ....................................................... 308
4.2 Intel
®
I/O Acceleration Technology (Intel
®
IOAT)................................................ 308
4.2.1 Intel
®
QuickData Technology................................................................. 309
4.2.1.1 Port/Stream Priority .............................................................. 309
4.2.1.2 Write Combining................................................................... 309
4.2.1.3 Marker Skipping.................................................................... 309
4.2.1.4 Buffer Hint........................................................................... 309
4.2.1.5 DCA.................................................................................... 309
4.2.1.6 DMA.................................................................................... 309
4.3 Simultaneous Multi Threading (SMT).................................................................. 311
4.4 Intel
®
Turbo Boost Technology ......................................................................... 311
5.0 IIO Ordering Model ............................................................................................... 312
5.1 Introduction ................................................................................................... 312
5.2 Inbound Ordering Rules ................................................................................... 313
5.2.1 Inbound Ordering Requirements............................................................. 313
5.2.2 Special Ordering Relaxations.................................................................. 314
5.2.2.1 Inbound Writes Can Pass Outbound Completions....................... 314
5.2.2.2 PCI Express Relaxed Ordering................................................. 314
5.2.3 Inbound Ordering Rules Summary.......................................................... 315
5.3 Outbound Ordering Rules ................................................................................. 315
5.3.1 Outbound Ordering Requirements........................................................... 315
5.3.2 Outbound Ordering Rules Summary........................................................ 316
5.4 Peer-to-Peer Ordering Rules ............................................................................. 317
5.4.1 Hinted Peer-to-Peer.............................................................................. 317
5.4.2 Local Peer-to-Peer................................................................................ 317
5.4.3 Remote Peer-to-Peer ............................................................................ 318
5.5 Interrupt Ordering Rules .................................................................................. 318
5.5.1 SpcEOI Ordering .................................................................................. 318
5.5.2 SpcINTA Ordering ................................................................................ 318