Datasheet
Intel
®
Xeon
®
Processor C5500/C3500 Series
February 2010 Datasheet, Volume 1
Order Number: 323103-001 109
Interfaces
2.4.7 Intel
®
QuickPath Interconnect Address Decoding
On past FSB platforms, the processors and I/O subsystem could direct all memory and
I/O accesses to the North Bridge. The processor’s Intel
®
QuickPath Interconnect is
more distributed in nature. The memory controller is integrated inside the processor.
Therefore, a processor may be able to resolve memory accesses locally or may have to
send it to another processor.
Each Intel
®
QuickPath Interconnect agent that is capable of accessing a system
resource (system memory, MMIO, etc) needs a way to determine the Intel
®
QuickPath
Interconnect agent that owns that resource. This is accomplished by Source Address
Decoders (SAD). Each Intel
®
QuickPath Interconnect agent contains a Source Address
Decoder whereby a lookup process is used to convert a physical address to the Node ID
of the Intel
®
QuickPath Interconnect agent that owns that address.
In some Intel
®
QuickPath Interconnect implementations, each Intel
®
QuickPath
Interconnect agent may have multiple Intel
®
QuickPath Interconnect links and needs to
know which of the links can be used to reach the target agent. This job is handled via a
Routing Table (RT). The Routing Table takes the target Node ID and provides a link
number. The target agent may then need to perform another level of lookup to
determine how to satisfy the request (e.g., a memory controller may need to determine
which of many memory channels contains the target address). This lookup structure is
called Target Address Decode (TAD).
The Intel
®
Xeon
®
processor C5500/C3500 series implements a fixed Intel
®
QuickPath
Interconnect routing topology that simplifies the SAD, RT and TAD structures and also
simplifies programming of these structures. Memory SAD entries in the processor
directly refer to a target package number and not a Node ID. The processor knows
which package is local and which is remote and therefore, either satisfies the request
internally, or sends it to the remote package over the processor-processor Intel
®
QuickPath Interconnect link.
2.4.8 Transport Layer
The Intel
®
QuickPath Interconnect Transport Layer is not implemented on the Intel
®
Xeon
®
processor C5500/C3500 series. The Transport layer is optional in the Intel
®
QuickPath architecture as defined.
2.4.9 Protocol Layer
The Protocol layer implements the higher level communication protocol between nodes,
such as cache coherence (reads, writes, invalidates), ordering, peer-to-peer I/O,
interrupt delivery etc. The write-invalidate protocol implements the MESIF states,
where the MESI states have the usual connotation (Modified, Exclusive, Shared,
Invalid), and the F state indicates a read-only forwarding state.
2.4.9.1 Protocol Layer Attributes
The processor’s Intel
®
QuickPath Interconnect Protocol layer attributes are
summarized in Table 57 through Table 62 below.