Datasheet

Interfaces
Intel
®
Xeon
®
Processor C5500/C3500 Series
Datasheet, Volume 1 February 2010
108 Order Number: 323103-001
2.4.4 Intel
®
QuickPath Interconnect Probing Considerations
When a Logic Analyzer probe is present on the Intel
®
QuickPath Interconnect links (for
hardware debug purposes), the characteristics of the Intel
®
QuickPath Interconnect
link are changed. This requires slightly different transmitter equalization parameters
and retraining period. It is expected that these alternate parameters will be stored in
BIOS. There is no mechanism for automatically detecting the presence of probes.
Therefore, the BIOS must be told if the probes are present in order to load the correct
equalization parameters. Using the incorrect set of equalization parameters (with
probes and without probes) will cause the platform to not boot reliably.
2.4.5 Link Layer
The Link layer abstracts the physical layer from the upper layers, and provides reliable
data transfer and flow control between two directly connected Intel
®
QuickPath
Interconnect entities. It is responsible for virtualization of a physical channel into
multiple virtual channels and message classes.
2.4.5.1 Link Layer Attributes
Intel
®
QuickPath Interconnect Link layer attributes are summarized in Table 55 below.
2.4.6 Routing Layer
The Routing layer provides a flexible and distributed way to route Intel
®
QuickPath
Interconnect packets from source to destination. The routing is based on the
destination. It relies on the virtual channel and message class abstraction of the link
layer to specify the Intel
®
QuickPath Interconnect port(s) and virtual network(s) on
which to route a packet. The mechanism for routing is defined through implementation
of routing tables.
2.4.6.1 Routing Layer Attributes
The Intel
®
QuickPath Interconnect Routing layer attributes are summarized in Table 56
below.
Table 55. Intel
®
QuickPath Interconnect Link Layer Attributes
Feature Support Notes
Number of Node IDs supported 4 Four for a DP system, two for a UP system.
Packet Format DP
Extended Header Support No
Virtual Networks Supported VN0, VNA
Viral indication No
Data Poisoning Yes
Simple CRC (8 bit) Yes
Rolling CRC (16 bit) No
Table 56. Intel
®
QuickPath Interconnect Routing Layer Attributes
Feature Support
Through routing capability for processors Yes