Datasheet

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Intel

Xeon

Processor C5500/C3500 Series

February 2010 Datasheet, Volume 1

Order Number: 323103-001 107

Interfaces

2.4.2 Physical Layer Implementation

The physical layer of the Intel

QPI bus is the physical entity between two components,

it uses a differential signalling scheme, and is responsible for the electrical transfer of

data.

2.4.2.1 Processor’s Intel

QuickPath Interconnect Physical Layer Attributes

The processor’s Intel

QuickPath Interconnect Physical layer attributes are summarized

in Table 54 below.

2.4.3 Processor’s Intel

QuickPath Interconnect Link Speed

Configuration

Intel

QuickPath Interconnect link initialization is performed following a VCCPWRGOOD

reset. At reset, the Intel

QuickPath Interconnect links come up in slow mode

(66 MT/s). BIOS must then determine the speed at which to run the Intel

QuickPath

Interconnect links in full speed mode, program the transmitter equalization parameters

and issue a processor-only reset to bring the Intel

QuickPath Interconnect links to full

speed. The equalization parameters are dependent on the specific board design, and it

is expected these parameters will be hard coded in the BIOS. Once the Intel

QuickPath Interconnect links transition to full speed, they cannot go back to slow mode

without a VCCPWRGOOD reset.

The maximum supported Intel

QuickPath Interconnect link speed is processor SKU

dependent.

2.4.3.1 Detect Intel

QuickPath Interconnect Speeds Supported by the

Processors

The BIOS can detect the minimum and maximum Intel

QuickPath Interconnect data

rate supported by a processor. This information is indicated by the following processor

CSRs: QPI_0_PLL_STATUS and QPI_1_PLL_STATUS. The BSP can also read the CSRs of

the other processor, without assistance from the other processor. Both processors must

be initialized to the same Intel

QuickPath Interconnect data rates.

Table 54. Processor’s Intel

QuickPath Interconnect Physical Layer Attributes

Feature Supported Notes

Support for full width (20 bit) links Yes

Support for half width (10 bit) links No

Support for quarter width (5 bit) links No

Link Self Healing No

Clock channel failover No

Lane Reversal Yes

Polarity Reversal Yes

Hot-Plug support No

Independent control of link width in each

direction

Link Power Management - L0s Yes

An adaptive L0s scheme, where the idle

threshold is continually adjusted by hardware.

The associated parameters are fixed at the

factory and do not require software

programming.

Link Power Management - L1 Yes