Datasheet

Interfaces
Intel
®
Xeon
®
Processor C5500/C3500 Series
Datasheet, Volume 1 February 2010
106 Order Number: 323103-001
Data needing to go between processors is converted into packets that are transmitted
serially over the Intel
®
QPI bus, rather than previous Intel architectures that used the
parallel 64-bit Front Side Bus (FSB). Intel
®
Xeon
®
processor C5500/C3500 series SKUs
are available supporting various Intel
®
QPI link data rates.
The Intel
®
QuickPath Interconnect architecture is partitioned into five layers, one of
which is optional depending on the platform specifics. Section 2.4.2 through
Section 2.4.9.1 provide an overview of each of the layers.
Figure 43. Intel
®
Xeon
®
Processor C5500/C3500 Series Dual Processor Configuration
Block Diagram
QPI Bus
Bifurcatible
x16 PCIe
Dual Function
x4 DMI/PCIe
Dual Function
x4 DMI/PCIe
Bifurcatible
x16 PCIe
DDR3 Memory
Bus x3
DDR3 Memory
Bus x3
Intel Xeon Processor
C5500/C3500 Series
(Legacy Socket)
Intel Xeon Processor
C5500/C3500 Series
(Non-Legacy Socket)
PCH