Datasheet

Intel
®
Xeon
®
Processor C5500/C3500 Series
February 2010 Datasheet, Volume 1
Order Number: 323103-001 103
Interfaces
2.3.9.4 Configuration and Memory Write Protocol
Configuration and memory writes are accomplished through a series of SMBus writes.
As with configuration reads, a write sequence is first used to initialize the Bus Number,
Device, Function, and Register Number for the configuration access. The writing of this
information can be accomplished through any combination of the supported SMBus
write commands (Block, Word or Byte).
Note: On the SMBus, there is no concept of byte enables. Therefore, the Register Number
written to the slave is assumed to be aligned to the length of the Internal Command. In
other words, for a Write Byte internal command, the Register Number specifies the
byte address. For a Write DWord internal command, the two least-significant bits of the
Register Number or Address Offset are ignored. This is different from PCI where the
byte enables are used to indicate the byte of interest.
After all the information is set up, the SMBus master initiates one or more writes that
sets up the data to be written. The final write (End bit is set) initiates an internal
configuration write. The slave interface could potentially clock stretch the last data
write until the write completes without error. If an error occurred, the SMBus interface
NACKs the last write operation just before the stop bit.
The busy bit will be set for the write transaction. A config write to the IIO will most
likely complete before the SMBus master can poll the busy bit. If the transaction is
destined to a chip on a PCIe link then it could take several more clock cycle to complete
the outbound transaction being sent.
Examples of configuration writes are illustrated below. For the definition of the diagram
conventions below, see the SMBus Specification, Revision 2.0.
2.3.9.5 SMBus Configuration and Memory Block Writes
Figure 37. SMBus Block-Size Configuration Register Write
S 1110_1X0 W A Cmd = 11011110 A
Rsv[3:0] & Addr[11:8] A Regoff [7:0] A
Byte cnt = 4 A
Data [31:24] A
Bus Num A Dev / Func A
Data [23:16] A Data [15:8] A
Data [7:0] A PEC A P
Figure 38. SMBus Block-Size Memory Register Write
S 1110_1X0 W A Cmd = 11111110 A
Addr [15:8] A Addr [7:0] A
Byte cnt = 4 A
Data [31:24] A
Mem Region A Addr [23:16] A
Data [23:16] A Data [15:8] A
Data [7:0] A PEC A P