Datasheet

Intel
®
Xeon
®
Processor C5500/C3500 Series
February 2010 Datasheet, Volume 1
Order Number: 323103-001 101
Interfaces
2.3.9.3 SMBus Configuration and Memory Byte Reads
Figure 35. SMBus Byte-Size Configuration Register Read
S 1110_1X0 W A Cmd = 10010000 A Bus Num A
Write address
for a Read
squence
S 1110_1X0 W A Cmd = 10010000 A
Sr
1110_1X0 R A Status A
Read Sequence
Poll until
Status[7] = 0
PEC
S 1110_1X0 W A Cmd = 00010000 A
A P
PEC N P
S 1110_1X0 W A Cmd = 00010000 A
Sr
1110_1X0 R A
S 1110_1X0 W A Cmd = 01010000 A
Sr
1110_1X0 R A Data [7:0] A PEC N P
S 1110_1X0 W A Cmd = 00010000 A
S 1110_1X0 W A Cmd = 01010000 A
Rsv[3:0] & Addr[11:8]
Regoff [7:0] A
A PEC A P
PEC A P
Dev / Func A PEC A P
S 1110_1X0 W A Cmd = 00010000 A
Sr
1110_1X0 R A Data [23:16] A PEC N P
S 1110_1X0 W A Cmd = 00010000 A
Sr
1110_1X0 R A
Data [31:24] A PEC N P
Data [15:8] A PEC N P