Datasheet
Intel
®
Xeon
®
Processor C5500/C3500 Series
Datasheet, Volume 1 February 2010
10 Order Number: 323103-001
3.20.2.13 SB45BASE: Secondary BAR 4/5 Base Address ...........................249
3.20.2.14 SUBVID: Subsystem Vendor ID (Dev#3, PCIE NTB Sec Mode) .....250
3.20.2.15 SID: Subsystem Identity (Dev#3, PCIE NTB Sec Mode)..............250
3.20.2.16 CAPPTR: Capability Pointer .....................................................250
3.20.2.17 INTL: Interrupt Line Register ..................................................251
3.20.2.18 INTPIN: Interrupt Pin Register.................................................251
3.20.2.19 MINGNT: Minimum Grant Register ...........................................252
3.20.2.20 MAXLAT: Maximum Latency Register........................................252
3.20.3 Device-Specific PCI Configuration Space - 0x40 to 0xFF.............................252
3.20.3.1 MSICAPID: MSI Capability ID..................................................252
3.20.3.2 MSINXTPTR: MSI Next Pointer.................................................252
3.20.3.3 MSICTRL: MSI Control Register ...............................................253
3.20.3.4 MSIAR: MSI Lower Address Register ........................................254
3.20.3.5 MSIUAR: MSI Upper Address Register ......................................254
3.20.3.6 MSIDR: MSI Data Register......................................................255
3.20.3.7 MSIMSK: MSI Mask Bit Register ..............................................256
3.20.3.8 MSIPENDING: MSI Pending Bit Register....................................256
3.20.3.9 MSIXCAPID: MSI-X Capability ID.............................................257
3.20.3.10 MSIXNXTPTR: MSI-X Next Pointer............................................257
3.20.3.11 MSIXMSGCTRL: MSI-X Message Control Register.......................257
3.20.3.12 TABLEOFF_BIR: MSI-X Table Offset and BAR Indicator Register
(BIR).....................................................................................258
3.20.3.13 PBAOFF_BIR: MSI-X Pending Bit Array Offset and BAR Indicator..259
3.20.3.14 PXPCAPID: PCI Express Capability Identity Register ...................259
3.20.3.15 PXPNXTPTR: PCI Express Next Pointer Register .........................260
3.20.3.16 PXPCAP: PCI Express Capabilities Register ................................260
3.20.3.17 DEVCAP: PCI Express Device Capabilities Register .....................261
3.20.3.18 DEVCTRL: PCI Express Device Control Register (PCIE NTB
Secondary).............................................................................263
3.20.3.19 DEVSTS: PCI Express Device Status Register ............................265
3.20.3.20 LNKCAP: PCI Express Link Capabilities Register .........................266
3.20.3.21 LNKCON: PCI Express Link Control Register ..............................268
3.20.3.22 LNKSTS: PCI Express Link Status Register ................................270
3.20.3.23 DEVCAP2: PCI Express Device Capabilities Register 2.................272
3.20.3.24 DEVCTRL2: PCI Express Device Control Register 2.....................272
3.20.3.25 SSCNTL: Secondary Side Control.............................................274
3.20.3.26 PMCAP: Power Management Capabilities Register.......................274
3.20.3.27 PMCSR: Power Management Control and Status Register ............275
3.20.3.28 SEXTCAPHDR: Secondary Extended Capability Header................276
3.21 NTB MMIO Space.............................................................................................277
3.21.1 NTB Shadowed MMIO Space...................................................................277
3.21.1.1 PBAR2LMT: Primary BAR 2/3 Limit...........................................279
3.21.1.2 PBAR4LMT: Primary BAR 4/5 Limit...........................................280
3.21.1.3 PBAR2XLAT: Primary BAR 2/3 Translate ...................................281
3.21.1.4 PBAR4XLAT: Primary BAR 4/5 Translate ...................................281
3.21.1.5 SBAR2LMT: Secondary BAR 2/3 Limit.......................................282
3.21.1.6 SBAR4LMT: Secondary BAR 4/5 Limit.......................................283
3.21.1.7 SBAR2XLAT: Secondary BAR 2/3 Translate ...............................284
3.21.1.8 SBAR4XLAT: Secondary BAR 4/5 Translate ...............................285
3.21.1.9 SBAR0BASE: Secondary BAR 0/1 Base Address .........................285
3.21.1.10 SBAR2BASE: Secondary BAR 2/3 Base Address .........................286
3.21.1.11 SBAR4BASE: Secondary BAR 4/5 Base Address .........................287
3.21.1.12 NTBCNTL: NTB Control...........................................................288
3.21.1.13 SBDF: Secondary Bus, Device and Function ..............................290
3.21.1.14 CBDF: Captured Bus, Device and Function ................................290
3.21.1.15 PDOORBELL: Primary Doorbell ................................................291
3.21.1.16 PDBMSK: Primary Doorbell Mask .............................................292
3.21.1.17 SDOORBELL: Secondary Doorbell ............................................292
3.21.1.18 SDBMSK: Secondary Doorbell Mask .........................................292
3.21.1.19 USMEMMISS: Upstream Memory Miss ......................................292