Intel® Core™ i7 Processor Extreme Edition and Intel® Core™ i7 Processor Datasheet, Volume 1 November 2008 Document # 320834-001
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Contents 1 Introduction .............................................................................................................. 9 1.1 Terminology ..................................................................................................... 10 1.2 References ....................................................................................................... 11 2 Electrical Specifications ........................................................................................... 13 2.
7.2 7.3 7.4 7.5 8 Clock Control and Low Power States .....................................................................89 7.2.1 Thread and Core Power State Descriptions .................................................90 7.2.2 Package Power State Descriptions .............................................................91 Sleep States .....................................................................................................92 ACPI P-States (Intel® Turbo Boost Technology) .....................
Tables 1-1 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 2-9 2-10 2-11 2-12 2-13 2-14 2-15 2-16 3-1 3-2 3-3 4-1 4-2 5-1 6-1 6-2 6-3 6-4 6-5 6-6 7-1 7-2 7-3 8-1 8-2 Datasheet References ....................................................................................................... 11 Voltage Identification Definition........................................................................... 15 Market Segment Selection Truth Table for MS_ID[2:0] ........................................... 17 Signal Groups .......
Datasheet
Intel® Core™ i7 Processor Extreme Edition and Intel® Core™ i7 Processor Features • Available at 3.20 GHz, 2.93 GHz, and 2.
Revision History Revision Number -001 Description • Initial release Date November 2008 § 8 Datasheet
Introduction 1 Introduction The Intel® Core™ i7 processor Extreme Edition and Intel® Core™ i7 processor are intended for high performance high-end desktop, Uni-processor (UP) server, and workstation systems. Several architectural and microarchitectural enhancements have been added to this processor including four processor cores in the processor package and increased shared cache.
Introduction The processor supports all the existing Streaming SIMD Extensions 2 (SSE2), Streaming SIMD Extensions 3 (SSE3) and Streaming SIMD Extensions 4 (SSE4). The processor supports several Advanced Technologies: Intel® 64 Technology (Intel® 64), Enhanced Intel SpeedStep® Technology, Intel® Virtualization Technology (Intel® VT), Intel® Turbo Boost Technology, and Intel® Hyper-Threading Technology. 1.
Introduction • Intel® 64 Architecture — An enhancement to Intel's IA-32 architecture, allowing the processor to execute operating systems and applications written to take advantage of Intel® 64. Further details on Intel® 64 architecture and programming model can be found at http://developer.intel.com/technology/intel64/. • Intel® Virtualization Technology (Intel® VT) — A set of hardware enhancements to Intel server and client platforms that can improve virtualization solutions.
Introduction 12 Datasheet
Electrical Specifications 2 Electrical Specifications 2.1 Intel® QPI Differential Signaling The processor provides an Intel QPI port for high speed serial transfer between other Intel QPI-enabled components. The Intel QPI port consists of two unidirectional links (for transmit and receive). Intel QPI uses a differential signalling scheme where pairs of opposite-polarity (D_P, D_N) signals are used. On-die termination (ODT) is provided on the processor silicon and termination is to VSS.
Electrical Specifications ensure that the voltage provided to the processor remains within the specifications listed in Table 2-7. Failure to do so can result in timing violations or reduced lifetime of the processor. 2.3.1 VCC, VTTA, VTTD, VDDQ Decoupling Voltage regulator solutions need to provide bulk capacitance and the baseboard designer must assure a low interconnect resistance from the regulator to the LGA1366 socket.
Electrical Specifications The processor uses eight voltage identification signals, VID[7:0], to support automatic selection of voltages. Table 2-1 specifies the voltage level corresponding to the state of VID[7:0]. A ‘1’ in this table refers to a high voltage level and a ‘0’ refers to a low voltage level. If the processor socket is empty (VID[7:0] = 11111111), or the voltage regulation circuit cannot supply the voltage that is requested, the voltage regulator must disable itself.
Electrical Specifications Table 2-1. Voltage Identification Definition (Sheet 2 of 3) VID 7 VID 6 VID 5 VID 4 VID 3 VID 2 VID 1 VID 0 VCC_MAX VID 7 VID 6 VID 5 VID 4 VID 3 VID 2 VID 1 VID 0 VCC_MAX 0 0 0 1 1 1 1 1 1.41875 0 1 1 1 1 0 1 0 0.85000 0 0 1 0 0 0 0 0 1.41250 0 1 1 1 1 0 1 1 0.84374 0 0 1 0 0 0 0 1 1.40625 0 1 1 1 1 1 0 0 0.83750 0 0 1 0 0 0 1 0 1.40000 0 1 1 1 1 1 0 1 0.83125 0 0 1 0 0 0 1 1 1.
Electrical Specifications Table 2-1. Voltage Identification Definition (Sheet 3 of 3) VID 7 VID 6 VID 5 VID 4 VID 3 VID 2 VID 1 VID 0 VCC_MAX VID 7 VID 6 VID 5 VID 4 VID 3 VID 2 VID 1 VID 0 VCC_MAX 0 1 0 0 1 1 1 1 1.11875 1 0 1 0 1 0 1 0 0.55000 0 1 0 1 0 0 0 0 1.11250 1 0 1 0 1 0 1 1 0.54375 0 1 0 1 0 0 0 1 1.10625 1 0 1 0 1 1 0 0 0.53750 0 1 0 1 0 0 1 0 1.10000 1 0 1 0 1 1 0 1 0.53125 0 1 0 1 0 0 1 1 1.
Electrical Specifications 2.7 Signal Groups Signals are grouped by buffer type and similar characteristics as listed in Table 2-3. The buffer type indicates which signaling technology and specifications apply to the signals. All the differential signals, and selected DDR3 and Control Sideband signals have OnDie Termination (ODT) resistors. There are some signals that do not have ODT and need to be terminated on the board. The signals that have ODT are listed in Table 2-4. Table 2-3.
Electrical Specifications Table 2-3. Signal Groups (Sheet 2 of 2) Signal Group Signals1,2 Type Single ended CMOS Output VTT_VID[4:2] Single ended Analog Input ISENSE Reset Input RESET# Asynchronous Input VCCPWRGOOD, VTTPWRGOOD, VDDPWRGOOD Power VCC, VTTA, VTTD, VCCPLL, VDDQ Asynchronous CMOS Output PSI# Sense Points VCC_SENSE, VSS_SENSE Other SKTOCC#, DBR# Reset Signal Single ended PWRGOOD Signals Single ended Power/Other 1. 2. Table 2-4. Refer to Chapter 5 for signal descriptions.
Electrical Specifications 2.9 Platform Environmental Control Interface (PECI) DC Specifications PECI is an Intel proprietary interface that provides a communication channel between Intel processors and chipset components to external thermal monitoring devices. The processor contains a Digital Thermal Sensor (DTS) that reports a relative die temperature as an offset from Thermal Control Circuit (TCC) activation temperature.
Electrical Specifications 2.9.2 Input Device Hysteresis The input buffers in both client and host models must use a Schmitt-triggered input design for improved noise immunity. Use Figure 2-2 as a guide for input buffer design. Figure 2-2. Input Device Hysteresis VTTD Maximum VP PECI High Range Minimum VP Minimum Hysteresis Valid Input Signal Range Maximum VN Minimum VN PECI Low Range PECI Ground 2.
Electrical Specifications . Table 2-6. Processor Absolute Minimum and Maximum Ratings Symbol Parameter Min Max Unit Notes1, 2 VCC Processor Core voltage with respect to VSS -0.3 1.55 V VTTA Voltage for the analog portion of the integrated memory controller, QPI link and Shared Cache with respect to VSS — 1.35 V 3 VTTD Voltage for the digital portion of the integrated memory controller, QPI link and Shared Cache with respect to VSS — 1.
Electrical Specifications 2.11.1 DC Voltage and Current Specification Table 2-7. Voltage and Current Specifications Symbol 3. 4. 5. Typ Max Unit Notes 1 0.8 — 1.
Electrical Specifications Table 2-8. VCC Static and Transient Tolerance 1. 2. 3. 24 ICC (A) VCC_Max (V) VCC_Typ (V) VCC_Min (V) Notes 0 VID - 0.000 VID - 0.019 VID - 0.038 1, 2, 3 5 VID - 0.004 VID - 0.023 VID - 0.042 1, 2, 3 10 VID - 0.008 VID - 0.027 VID - 0.046 1, 2, 3 15 VID - 0.012 VID - 0.031 VID - 0.050 1, 2, 3 20 VID - 0.016 VID - 0.035 VID - 0.054 1, 2, 3 25 VID - 0.020 VID - 0.039 VID - 0.058 1, 2, 3 30 VID - 0.024 VID - 0.043 VID - 0.
Electrical Specifications Figure 2-3. VCC Static and Transient Tolerance Load Lines Icc [A] 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 VID - 0.000 VID - 0.013 VID - 0.025 Vcc Maximum VID - 0.038 VID - 0.050 VID - 0.063 VID - 0.075 Vcc Typical V VID - 0.088 c c VID - 0.100 V VID - 0.113 Vcc Minimum VID - 0.125 VID - 0.138 VID - 0.150 VID - 0.163 VID - 0.175 Table 2-9.
Electrical Specifications Table 2-10. VTT Static and Transient Tolerance ITT (A) VTT_Max (V) VTT_Typ (V) VTT_Min (V) 0 VID + 0.0315 VID – 0.0000 VID – 0.0315 1 VID + 0.0255 VID – 0.0060 VID – 0.0375 2 VID + 0.0195 VID – 0.0120 VID – 0.0435 3 VID + 0.0135 VID – 0.0180 VID – 0.0495 4 VID + 0.0075 VID – 0.0240 VID – 0.0555 5 VID + 0.0015 VID – 0.0300 VID – 0.0615 6 VID – 0.0045 VID – 0.0360 VID – 0.0675 7 VID – 0.0105 VID – 0.0420 VID – 0.0735 8 VID – 0.0165 VID – 0.
Electrical Specifications Figure 2-4. VTT Static and Transient Tolerance Load Line Itt [A] (sum of Itta and Ittd) 0 5 10 15 20 25 0.0500 0.0375 0.0250 0.0125 0.0000 V t t V -0.0125 Vtt Maximum -0.0250 -0.0375 -0.0500 -0.0625 -0.0750 -0.0875 Vtt Typical -0.1000 -0.1125 -0.1250 Vtt Minimum -0.1375 -0.1500 -0.1625 -0.1750 -0.1875 -0.2000 -0.2125 Table 2-11.
Electrical Specifications 4. 5. VIH and VOH may experience excursions above VDDQ. However, input signal drivers must comply with the signal quality specifications. COMP resistance must be provided on the system board with 1% resistors. See the applicable platform design guide for implementation details. DDR_COMP[2:0] resistors are to VSS. Table 2-12. RESET# Signal DC Specifications Symbol Parameter Min Typ Max Units V VIL Input Low Voltage — — 0.40 * VTTA VIH Input High Voltage 0.
Electrical Specifications Table 2-15. Control Sideband Signal Group DC Specifications Symbol Parameter Min Typ Max Units Notes1 VIL Input Low Voltage — — 0.64 * VTTA V 2 VIH Input High Voltage 0.76 * VTTA — — V 2 VOL Output Low Voltage — — VTTA * RON / (RON + Rsys_term) V 2,4 VOH Output High Voltage VTTA — — V 2,4 Ron Buffer on Resistance 10 — 18 Ω Ron Buffer on Resistance for VID[7:0] — 100 — — — ± 200 μA 3 49.4 49.9 50.
Electrical Specifications Figure 2-5. VCC Overshoot Example Waveform Example Overshoot Waveform Voltage (V) VID + VOS VOS VID TOS Time TOS: Overshoot time above VID VOS: Overshoot above VID 2.11.3 Die Voltage Validation Core voltage (VCC) overshoot events at the processor must meet the specifications in Table 2-16 when measured across the VCC_SENSE and VSS_SENSE lands. Overshoot events that are < 10 ns in duration may be ignored.
Package Mechanical Specifications 3 Package Mechanical Specifications The processor is packaged in a Flip-Chip Land Grid Array package that interfaces with the motherboard via an LGA1366 socket. The package consists of a processor mounted on a substrate land-carrier. An integrated heat spreader (IHS) is attached to the package substrate and core and serves as the mating surface for processor thermal solutions, such as a heatsink.
Package Mechanical Specifications Figure 3-2.
Package Mechanical Specifications Figure 3-3.
Package Mechanical Specifications 3.2 Processor Component Keep-Out Zones The processor may contain components on the substrate that define component keepout zone requirements. A thermal and mechanical solution design must not intrude into the required keep-out zones. Decoupling capacitors are typically mounted to either the topside or land-side of the package substrate. See Figure 3-2 and Figure 3-3 for keepout zones.
Package Mechanical Specifications 3.6 Processor Mass Specification The typical mass of the processor is 35g. This mass [weight] includes all the components that are included in the package. 3.7 Processor Materials Table 3-3 lists some of the package components and associated materials. Table 3-3. Processor Materials Component 3.
Package Mechanical Specifications 3.9 Processor Land Coordinates Figure 3-5 shows the top view of the processor land coordinates. The coordinates are referred to throughout the document to identify processor lands. Figure 3-5.
Land Listing 4 Land Listing This section provides sorted land list in Table 4-1 and Table 4-2. Table 4-1 is a listing of all processor lands ordered alphabetically by land name. Table 4-2 is a listing of all processor lands ordered by land number. Table 4-1. Land Listing by Land Name (Sheet 1 of 36) Land Name BCLK_DN Land No. AH35 Table 4-1. Land Listing by Land Name (Sheet 2 of 36) Buffer Type Direction CMOS I DDR0_CLK_P[0] Land Name Land No.
Land Listing Table 4-1. Land Listing by Land Name (Sheet 3 of 36) Land Name Land No. Buffer Type Direction Table 4-1. Land Listing by Land Name (Sheet 4 of 36) Land Name Land No.
Land Listing Table 4-1. Land Listing by Land Name (Sheet 5 of 36) Buffer Type Direction D32 CMOS O DDR1_DQ[24] H33 DDR0_WE# B13 CMOS O DDR1_DQ[25] L33 CMOS I/O DDR1_BA[0] C18 CMOS O DDR1_DQ[26] K32 CMOS I/O DDR1_BA[1] K13 CMOS O DDR1_DQ[27] J32 CMOS I/O DDR1_BA[2] H27 CMOS O DDR1_DQ[28] J34 CMOS I/O Land Name DDR0_RESET# Land No. Table 4-1. Land Listing by Land Name (Sheet 6 of 36) Land Name Land No.
Land Listing Table 4-1. Land Listing by Land Name (Sheet 7 of 36) Land Name Land No. Buffer Type Direction Table 4-1. Land Listing by Land Name (Sheet 8 of 36) Land Name Land No.
Land Listing Table 4-1. Land Listing by Land Name (Sheet 9 of 36) Land Name Land No. Table 4-1. Land Listing by Land Name (Sheet 10 of 36) Buffer Type Direction CMOS I/O DDR2_DQ[54] Land Name Land No.
Land Listing Table 4-1. Land Listing by Land Name (Sheet 11 of 36) Land Name Land No. Buffer Type Direction Table 4-1. Land Listing by Land Name (Sheet 12 of 36) Land Name Land No.
Land Listing Table 4-1. Land Listing by Land Name (Sheet 13 of 36) Land Name Land No. Buffer Type Direction Table 4-1. Land Listing by Land Name (Sheet 14 of 36) Land Name Land No.
Land Listing Table 4-1. Land Listing by Land Name (Sheet 15 of 36) Land Name Land No. Buffer Type Table 4-1. Land Listing by Land Name (Sheet 16 of 36) Direction Land Name Land No.
Land Listing Table 4-1. Land Listing by Land Name (Sheet 17 of 36) Land Name Land No. Buffer Type Table 4-1. Land Listing by Land Name (Sheet 18 of 36) Direction Land Name Land No.
Land Listing Table 4-1. Land Listing by Land Name (Sheet 19 of 36) Land Name Land No. Buffer Type Table 4-1. Land Listing by Land Name (Sheet 20 of 36) Direction Land Name Land No.
Land Listing Table 4-1. Land Listing by Land Name (Sheet 21 of 36) Land Name Land No. Buffer Type Table 4-1. Land Listing by Land Name (Sheet 22 of 36) Direction Land Name Land No.
Land Listing Table 4-1. Land Listing by Land Name (Sheet 23 of 36) Land Name Land No. Buffer Type Table 4-1. Land Listing by Land Name (Sheet 24 of 36) Direction Land Name Land No.
Land Listing Table 4-1. Land Listing by Land Name (Sheet 25 of 36) Land Name Land No. Buffer Type Direction Table 4-1. Land Listing by Land Name (Sheet 26 of 36) Land Name Land No.
Land Listing Table 4-1. Land Listing by Land Name (Sheet 27 of 36) Land Name Land No. Buffer Type Table 4-1. Land Listing by Land Name (Sheet 28 of 36) Direction Land Name Land No.
Land Listing Table 4-1. Land Listing by Land Name (Sheet 29 of 36) Land Name Land No. Buffer Type Table 4-1. Land Listing by Land Name (Sheet 30 of 36) Direction Land Name Land No.
Land Listing Table 4-1. Land Listing by Land Name (Sheet 31 of 36) Land Name Land No. Buffer Type Table 4-1. Land Listing by Land Name (Sheet 32 of 36) Direction Land Name Land No.
Land Listing Table 4-1. Land Listing by Land Name (Sheet 33 of 36) Land Name Land No. Buffer Type Table 4-1. Land Listing by Land Name (Sheet 34 of 36) Direction Land Name Land No.
Land Listing Table 4-1. Land Listing by Land Name (Sheet 35 of 36) Land Name Land No. Buffer Type Table 4-1. Land Listing by Land Name (Sheet 36 of 36) Direction Land Name Land No.
Land Listing Table 4-2. Land Listing by Land Number (Sheet 1 of 36) Land No. Pin Name Table 4-2. Land Listing by Land Number (Sheet 2 of 36) Buffer Type Direction Land No.
Land Listing Table 4-2. Land Listing by Land Number (Sheet 3 of 36) Land No. Pin Name Buffer Type Table 4-2. Land Listing by Land Number (Sheet 4 of 36) Direction Land No.
Land Listing Table 4-2. Land Listing by Land Number (Sheet 5 of 36) Land No. AF9 Pin Name VTTD Buffer Type Direction PWR AG1 RSVD AG10 TMS TAP AG11 VSS GND AG2 RSVD AG3 VSS AG33 VSS I Table 4-2. Land Listing by Land Number (Sheet 6 of 36) Land No.
Land Listing Table 4-2. Land Listing by Land Number (Sheet 7 of 36) Land No. Pin Name Buffer Type Direction Table 4-2. Land Listing by Land Number (Sheet 8 of 36) Land No.
Land Listing Table 4-2. Land Listing by Land Number (Sheet 9 of 36) Land No. AM12 Pin Name Buffer Type Direction Table 4-2. Land Listing by Land Number (Sheet 10 of 36) Land No.
Land Listing Table 4-2. Land Listing by Land Number (Sheet 11 of 36) Land No. Pin Name Buffer Type Direction Table 4-2. Land Listing by Land Number (Sheet 12 of 36) Land No.
Land Listing Table 4-2. Land Listing by Land Number (Sheet 13 of 36) Land No. Pin Name Buffer Type AR37 RSVD AR38 QPI_DRX_DN[19] QPI AR39 VSS GND Direction Table 4-2. Land Listing by Land Number (Sheet 14 of 36) Land No.
Land Listing Table 4-2. Land Listing by Land Number (Sheet 15 of 36) Land No. Pin Name Buffer Type Direction Table 4-2. Land Listing by Land Number (Sheet 16 of 36) Land No.
Land Listing Table 4-2. Land Listing by Land Number (Sheet 17 of 36) Land No. Pin Name AW22 VSS AW23 AW24 Buffer Type Direction Table 4-2. Land Listing by Land Number (Sheet 18 of 36) Land No.
Land Listing Table 4-2. Land Listing by Land Number (Sheet 19 of 36) Land No. Pin Name Table 4-2. Land Listing by Land Number (Sheet 20 of 36) Buffer Type Direction Land No.
Land Listing Table 4-2. Land Listing by Land Number (Sheet 21 of 36) Land No. Pin Name Table 4-2. Land Listing by Land Number (Sheet 22 of 36) Buffer Type Direction Land No.
Land Listing Table 4-2. Land Listing by Land Number (Sheet 23 of 36) Land No. Pin Name Table 4-2. Land Listing by Land Number (Sheet 24 of 36) Buffer Type Direction Land No.
Land Listing Table 4-2. Land Listing by Land Number (Sheet 25 of 36) Land No. Pin Name Table 4-2. Land Listing by Land Number (Sheet 26 of 36) Buffer Type Direction Land No.
Land Listing Table 4-2. Land Listing by Land Number (Sheet 27 of 36) Land No. Pin Name Table 4-2. Land Listing by Land Number (Sheet 28 of 36) Buffer Type Direction Land No.
Land Listing Table 4-2. Land Listing by Land Number (Sheet 29 of 36) Land No. K34 Pin Name Buffer Type Direction RSVD DDR1_DQ[18] CMOS K36 VSS GND RSVD K38 DDR2_DQ[23] Land No. L30 K35 K37 Table 4-2.
Land Listing Table 4-2. Land Listing by Land Number (Sheet 31 of 36) Land No. Pin Name Buffer Type Direction Table 4-2. Land Listing by Land Number (Sheet 32 of 36) Land No.
Land Listing Table 4-2. Land Listing by Land Number (Sheet 33 of 36) Land No. Table 4-2. Land Listing by Land Number (Sheet 34 of 36) Buffer Type Direction Land No.
Land Listing Table 4-2. Land Listing by Land Number (Sheet 35 of 36) Land No. Pin Name Buffer Type Table 4-2. Land Listing by Land Number (Sheet 36 of 36) Direction Land No.
Signal Definitions 5 Signal Definitions 5.1 Signal Definitions Table 5-1. Signal Definitions (Sheet 1 of 4) Name Type Description BCLK_DN BCLK_DP I Differential bus clock input to the processor. BCLK_ITP_DN BCLK_ITP_DP O Buffered differential bus clock pair to ITP. BPM#[7:0] I/O BPM#[7:0] are breakpoint and performance monitor signals. They are outputs from the processor which indicate the status of breakpoints and programmable counters used for monitoring processor performance.
Signal Definitions Table 5-1. Signal Definitions (Sheet 2 of 4) Name Type Description DDR{0/1/2}_MA[15:0] O Selects the Row address for Reads and writes, and the column address for activates. Also used to set values for DRAM configuration registers. DDR{0/1/2}_ODT[3:0] O Enables various combinations of termination resistance in the target and nontarget DIMMs when data is read or written DDR{0/1/2}_RAS# O Row Address Strobe. DDR{0/1/2}_RESET# O Resets DRAMs.
Signal Definitions Table 5-1. Signal Definitions (Sheet 3 of 4) Name Type Description THERMTRIP# O Assertion of THERMTRIP# (Thermal Trip) indicates the processor junction temperature has reached a level beyond which permanent silicon damage may occur. Measurement of the temperature is accomplished through an internal thermal sensor.
Signal Definitions Table 5-1. Name Signal Definitions (Sheet 4 of 4) Type Description VTT_VID[4:2] O VTT_VID[2:4] (VTTVoltage ID) are used to support automatic selection of power supply voltages (VTT). VTT_SENSE VSS_SENSE_VTT O O VTT_SENSE and VSS_SENSE_VTT provide an isolated, low impedance connection to the processor VTT voltage and ground. They can used to sense or measure voltage near the silicon.
Thermal Specifications 6 Thermal Specifications 6.1 Package Thermal Specifications The processor requires a thermal solution to maintain temperatures within its operating limits. Any attempt to operate the processor outside these operating limits may result in permanent damage to the processor and potentially other components within the system. Maintaining the proper thermal environment is key to reliable, long-term system operation.
Thermal Specifications Section 6.3. The temperature reported over PECI is always a negative value and represents a delta below the onset of thermal control circuit (TCC) activation, as indicated by PROCHOT# (see Section 6.2, Processor Thermal Features). Systems that implement fan speed control must be designed to use this data. Systems that do not alter the fan speed only need to guarantee the thermal solution provides the ΨCA that meets the TTV thermal profile specifications.
Thermal Specifications Figure 6-1. Processor Thermal Profile 70.0 y = 43.2 + 0.19 * P 65.0 TTV Tcase in C 60.0 55.0 50.0 45.0 40.0 0 10 20 30 40 50 60 70 80 90 100 110 120 130 TTV Power (W) Notes: 1. Refer to Table 6-2 for discrete points that constitute the thermal profile. 2. Refer to the appropriate processor Thermal and Mechanical Design Guidelines (see Section 1.2) for system and environmental implementation details. 3.
Thermal Specifications 6.1.1.1 Specification for Operation Where Digital Thermal Sensor Exceeds TCONTROL When the DTS value is less than TCONTROL the fan speed control algorithm can reduce the speed of the thermal solution fan. This remains the same as with the previous guidance for fan speed control. During operation where the DTS value is greater than TCONTROL, the fan speed control algorithm must drive the fan speed to meet or exceed the target thermal solution performance (ΨCA) shown in Table 6-3.
Thermal Specifications 6.1.2 Thermal Metrology The minimum and maximum TTV case temperatures (TCASE) are specified in Table 6-1, and Table 6-2 and are measured at the geometric top center of the thermal test vehicle integrated heat spreader (IHS). Figure 6-2 illustrates the location where TCASE temperature measurements should be made.
Thermal Specifications 6.2 Processor Thermal Features 6.2.1 Processor Temperature A new feature in the Intel Core™ i7 processor Extreme Edition and Intel Core™ i7 processor is a software readable field in the IA32_TEMPERATURE_TARGET register that contains the minimum temperature at which the TCC will be activated and PROCHOT# will be asserted.
Thermal Specifications 6.2.2.1 Frequency/VID Control When the Digital Temperature Sensor (DTS) reaches a value of 0 (DTS temperatures reported via PECI may not equal zero when PROCHOT# is activated, see Section 6.3 for further details), the TCC will be activated and the PROCHOT# signal will be asserted. This indicates the processors' temperature has met or exceeded the factory calibrated trip temperature and it will take action to reduce the temperature.
Thermal Specifications 6.2.2.2 Clock Modulation Clock modulation is a second method of thermal control available to the processor. Clock modulation is performed by rapidly turning the clocks off and on at a duty cycle that should reduce power dissipation by about 50% (typically a 30–50% duty cycle). Clocks often will not be off for more than 32 microseconds when the TCC is active. Cycle times are independent of processor frequency.
Thermal Specifications external source (e.g., a voltage regulator) to activate the TCC. The ability to activate the TCC via PROCHOT# can provide a means for thermal protection of system components. As an output, PROCHOT# (Processor Hot) will go active when the processor temperature monitoring sensor detects that one or more cores has reached its maximum safe operating temperature. This indicates that the processor Thermal Control Circuit (TCC) has been activated, if enabled.
Thermal Specifications 6.3.1.1 Fan Speed Control with Digital Thermal Sensor Fan speed control solutions use a value stored in the static variable, TCONTROL. The DTS temperature data which is delivered over PECI (in response to a GetTemp0() command) is compared to this TCONTROL reference. The DTS temperature is reported as a relative value versus an absolute value.
Thermal Specifications 6.3.2 PECI Specifications 6.3.2.1 PECI Device Address The PECI register resides at address 30h. 6.3.2.2 PECI Command Support The processor supports the PECI commands listed in Table 6-4. Table 6-4. Supported PECI Command Functions and Codes Command Function Code Ping() n/a GetTemp0() 01h Comments This command targets a valid PECI device address followed by zero Write Length and zero Read Length.
Thermal Specifications 6.4 Storage Conditions Specifications Environmental storage condition limits define the temperature and relative humidity limits to which the device is exposed to while being stored. The specified storage conditions are for component level prior to board attach (see following notes on post board attach limits).
Features 7 Features 7.1 Power-On Configuration (POC) Several configuration options can be configured by hardware. For electrical specifications on these options, refer to Chapter 2. Note that request to execute BIST is not selected by hardware but is passed across the Intel QPI link during initialization. The sampled information configures the processor for subsequent operation. These configuration options cannot be changed except by another reset.
Features Figure 7-1. Power States C0 MWAIT C1, HLT 2 2 2 MWAIT C1, HLT (C1E enabled) 2 MWAIT C3, I/O C3 1 1 C3 C1E C1 MWAIT C6, I/O C6 C6 1. No transition to C0 is needed to service a snoop when in C1 or C1E. , . 2. Transitions back to C0 occur on an interrupt or on access to monitored address (if state was entered via MWAIT). . 7.2.1 Thread and Core Power State Descriptions Individual threads may request low power states.
Features While in C1/C1E state, the processor will process bus snoops and snoops from the other threads. 7.2.1.3 C3 State Individual threads of the processor can enter the C3 state by initiating a P_LVL2 I/O read to the P_BLK or an MWAIT(C3) instruction. Before entering core C3, the processor flushes the contents of its caches. Except for the caches, the processor core maintains all its architectural state while in the C3 state. All of the clocks in the processor core are stopped in the C3 state.
Features If Intel QPI L1 has been granted, the processor will disable some clocks and PLLs and for processors with an integrated memory controller, the DRAM will be put into selfrefresh. 7.2.2.4 Package C6 State The package will enter the C6 low power state when all cores are in the C6 or lower power state and the processor has been granted permission by the other component(s) in the system to enter the C6 state.
Features 7.5 Enhanced Intel SpeedStep® Technology The processor features Enhanced Intel SpeedStep Technology. Following are the key features of Enhanced Intel SpeedStep Technology: • Multiple voltage and frequency operating points provide optimal performance at the lowest power.
Features 94 Datasheet
Boxed Processor Specifications 8 Boxed Processor Specifications 8.1 Introduction The processor will also be offered as an Intel boxed processor. Intel boxed processors are intended for system integrators who build systems from baseboards and standard components. The boxed processor will be supplied with a cooling solution. This chapter documents baseboard and system requirements for the cooling solution that will be supplied with the boxed processor.
Boxed Processor Specifications 8.2 Mechanical Specifications 8.2.1 Boxed Processor Cooling Solution Dimensions This section documents the mechanical specifications of the boxed processor. The boxed processor will be shipped with an unattached fan heatsink. Figure 8-1 shows a mechanical representation of the boxed processor. Clearance is required around the fan heatsink to ensure unimpeded airflow for proper cooling.
Boxed Processor Specifications Figure 8-3. Space Requirements for the Boxed Processor (top view) NOTES: 1. Diagram does not show the attached hardware for the clip design and is provided only as a mechanical representation. Figure 8-4.
Boxed Processor Specifications 8.2.2 Boxed Processor Fan Heatsink Weight The boxed processor fan heatsink will not weigh more than 550 grams. See Chapter 6 and the appropriate processor Thermal and Mechanical Design Guidelines (see Section 1.2). for details on the processor weight and heatsink requirements. 8.2.
Boxed Processor Specifications Table 8-1. Fan Heatsink Power and Signal Specifications Description Min Typ Max 10.8 12 13.2 - Peak steady-state fan current draw — — 3.0 A - Average steady-state fan current draw — — 2.0 A SENSE: SENSE frequency — 2 — pulses per fan revolution 1 CONTROL 21 25 28 kHz 2, 3 +12 V: 12 volt fan power supply Unit V Notes - IC: - 1. Baseboard should pull this pin up to 5V with a resistor. 2. Open drain type, pulse width modulated. 3.
Boxed Processor Specifications Figure 8-7. Boxed Processor Fan Heatsink Airspace Keepout Requirements (top view) Figure 8-8.
Boxed Processor Specifications 8.4.2 Variable Speed Fan If the boxed processor fan heatsink 4-pin connector is connected to a 3-pin motherboard header it will operate as follows: The boxed processor fan will operate at different speeds over a short range of internal chassis temperatures. This allows the processor fan to operate at a lower speed and noise level, while internal chassis temperatures are low.
Boxed Processor Specifications If the boxed processor fan heatsink 4-pin connector is connected to a 4-pin motherboard header and the motherboard is designed with a fan speed controller with PWM output (CONTROL see Table 8-1) and remote thermal diode measurement capability the boxed processor will operate as follows: As processor power has increased the required thermal solutions have generated increasingly more noise.
