Datasheet

Electrical Specifications
32 Datasheet
2.8.2 FSB Frequency Select Signals (BSEL[2:0])
The BSEL[2:0] signals are used to select the frequency of the processor input clock
(BCLK[1:0]). Ta b le 1 7 defines the possible combinations of the signals and the
frequency associated with each combination. The required frequency is determined by
the processor, chipset, and clock synthesizer. All agents must operate at the same
frequency.
The Intel
®
Core™2 Duo processor E7000 series operates at a 1333 MHz FSB and
1066 MHz FSB frequency (selected by a 333 MHz BCLK[1:0] or 266 MHz BCLK[1:0]
frequency). The Intel
®
Core™2 Duo processor E8000 series operates at a 1333 MHz
FSB frequency (selected by a 333 MHz BCLK[1:0] frequency). Individual processors will
only operate at their specified FSB frequency.
For more information about these signals, refer to Section 4.2.
2.8.3 Phase Lock Loop (PLL) and Filter
An on-die PLL filter solution will be implemented on the processor. The VCCPLL input is
used for the PLL. Refer to Table 4 for DC specifications.
2.8.4 BCLK[1:0] Specifications
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. Crossing voltage is defined as the instantaneous voltage value when the rising edge of
BCLK0 equals the falling edge of BCLK1.
3. “Steady state” voltage, not including overshoot or undershoot.
Table 17. BSEL[2:0] Frequency Table for BCLK[1:0]
BSEL2 BSEL1 BSEL0 FSB Frequency
L L L 266 MHz
L L H Reserved
L H H Reserved
L H L Reserved
H H L Reserved
H H H Reserved
H L H Reserved
H L L 333 MHz
Table 18. Front Side Bus Differential BCLK Specifications
Symbol Parameter Min Typ Max Unit Figure Notes
1
V
L
Input Low Voltage -0.30 N/A N/A V 4
V
H
Input High Voltage N/A N/A 1.15 V 4
V
CROSS(abs)
Absolute Crossing Point 0.300 N/A 0.550 V 4 2
ΔV
CROSS
Range of Crossing Points N/A N/A 0.140 V 4 -
V
OS
Overshoot N/A N/A 1.4 V 4 3
V
US
Undershoot -0.300 N/A N/A V 4 3
V
SWING
Differential Output Swing 0.300 N/A N/A V 5 4