Datasheet

Electrical Specifications
26 Datasheet
.
2.7.3.2 GTL+ Front Side Bus Specifications
In most cases, termination resistors are not required as these are integrated into the
processor silicon. See Table 8 for details on which GTL+ signals do not include on-die
termination.
Valid high and low levels are determined by the input buffers by comparing with a
reference voltage called GTLREF. Table 14 lists the GTLREF specifications. The GTL+
reference voltage (GTLREF) should be generated on the system board using high
precision voltage divider circuits.
Table 13. PECI DC Electrical Limits
Symbol Definition and Conditions Min Max Units Notes
1
NOTES:
1. V
TT
supplies the PECI interface. PECI behavior does not affect V
TT
min/max specifications. Refer to Table 4 for
V
TT
specifications.
V
in
Input Voltage Range -0.15 V
TT
V
V
hysteresis
Hysteresis 0.1 * V
TT
—V
2
2. The leakage specification applies to powered devices on the PECI bus.
V
n
Negative-edge threshold voltage 0.275 * V
TT
0.500 * V
TT
V
V
p
Positive-edge threshold voltage 0.550 * V
TT
0.725 * V
TT
V
I
source
High level output source
(V
OH
= 0.75 * V
TT)
-6.0 N/A mA
I
sink
Low level output sink
(V
OL
= 0.25 * V
TT
)
0.5 1.0 mA
I
leak+
High impedance state leakage to V
TT
N/A 50 µA
3
3. The input buffers use a Schmitt-triggered input design for improved noise immunity.
4. One node is counted for each client and one node for the system host. Extended trace lengths might appear
as additional nodes.
I
leak-
High impedance leakage to GND N/A 10 µA 3
C
bus
Bus capacitance per node N/A 10 pF 4
V
noise
Signal noise immunity above
300 MHz
0.1 * V
TT
—V
p-p