Intel® Pentium® Dual-Core Processor E6000 and E5000 Series Datasheet April 2010 Document Number: 320467-007
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Contents 1 Introduction .............................................................................................................. 9 1.1 Terminology ....................................................................................................... 9 1.1.1 Processor Terminology Definitions ............................................................ 10 1.2 References .......................................................................................................
5.3 Platform Environment Control Interface (PECI) ......................................................82 5.3.1 Introduction ...........................................................................................82 5.3.1.1 TCONTROL and TCC activation on PECI-Based Systems .....................82 5.3.2 PECI Specifications .................................................................................83 5.3.2.1 PECI Device Address..................................................................83 5.
Figures 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 Datasheet Processor VCC Static and Transient Tolerance............................................................... 20 VCC Overshoot Example Waveform ............................................................................. 21 Differential Clock Waveform ...................................................................................... 31 Measurement Points for Differential Clock Waveforms ...........................
Tables 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 6 References ..............................................................................................................11 Voltage Identification Definition ..................................................................................15 Absolute Maximum and Minimum Ratings ....................................................................17 Voltage and Current Specifications................................
Intel® Pentium® Dual-Core Processor E6000 and E5000 Series Features • Available at 2.80 GHz, 2.70 GHz, 2.66 GHz, 2.50 GHz (Intel® Pentium® Dual-Core processor E5000 series) • Available at 3.06 GHz, 2.93 GHz, and 2.
Revision History Revision Number -001 Description • Initial release Pentium® August 2008 -002 • Intel® -003 • Added Intel® Pentium® dual-core processor E5400 ® Revision Date dual-core processor E5300 Pentium ® December 2008 dual-core processor E6300 January 2009 -004 • Added Intel -005 • Added Intel® Pentium® dual-core processor E6500 August 2009 May 2009 -006 • Added Intel® Pentium® dual-core processor E6600 Januray 2010 -007 • Added Intel® Pentium® dual-core processor E5500
Introduction 1 Introduction The Intel® Pentium® dual-core processor E6000 and E5000 series are based on the Enhanced Intel® Core™ microarchitecture. The Intel Enhanced Core™ microarchitecture combines the performance of previous generation Desktop products with the power efficiencies of a low-power microarchitecture to enable smaller, quieter systems. The Intel Pentium dual-core processor E6000 and E5000 series are 64-bit processors that maintain compatibility with IA-32 software.
Introduction “Front Side Bus” refers to the interface between the processor and system core logic (also known as, the chipset components). The FSB is a multiprocessing interface to processors, memory, and I/O. 1.1.1 Processor Terminology Definitions Commonly used terms are explained here for clarification: • Intel® Pentium® dual-core processor E5000 series — Dual core processor in the FC-LGA8 package with a 2 MB L2 cache.
Introduction security of the system. See the Intel® 64 and IA-32 Architecture Software Developer's Manual for more detailed information. • Intel® 64 Architecture— An enhancement to the Intel IA-32 architecture, allowing the processor to execute operating systems and applications written to take advantage of the Intel 64 architecture. Further details on Intel 64 architecture and programming model are in the Intel Extended Memory 64 Technology Software Developer Guide at http://developer.intel.
Introduction 12 Datasheet
Electrical Specifications 2 Electrical Specifications This chapter describes the electrical characteristics of the processor interfaces and signals. DC electrical characteristics are provided. 2.1 Power and Ground Lands The processor has VCC (power), VTT, and VSS (ground) inputs for on-chip power distribution. All power lands must be connected to VCC, while all VSS lands must be connected to a system ground plane.
Electrical Specifications 2.2.3 FSB Decoupling The processor integrates signal termination on the die. In addition, some of the high frequency capacitance required for the FSB is included on the processor package. However, additional high frequency capacitance must be added to the motherboard to properly decouple the return currents from the front side bus. Bulk decoupling must also be provided by the motherboard for proper [A]GTL+ bus operation. 2.
Electrical Specifications Table 2. Voltage Identification Definition VID VID VID VID VID VID VID VID 7 6 5 4 3 2 1 0 Voltage VID VID VID VID VID VID VID VID Voltage 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 OFF 0 1 0 1 1 1 0 0 0 0 0 0 0 0 1 0 1.6 0 1 0 1 1 1 1 0 1.025 0 0 0 0 0 1 0 0 1.5875 0 1 1 0 0 0 0 0 1.0125 0 0 0 0 0 1 1 0 1.575 0 1 1 0 0 0 1 0 1 0 0 0 0 1 0 0 0 1.5625 0 1 1 0 0 1 0 0 0.9875 0 0 0 0 1 0 1 0 1.
Electrical Specifications 2.4 Reserved, Unused, and TESTHI Signals All RESERVED lands must remain unconnected. Connection of these lands to VCC, VSS, VTT, or to any other signal (including each other) can result in component malfunction or incompatibility with future processors. See Chapter 4 for a land listing of the processor and the location of all RESERVED lands.
Electrical Specifications 2.6 Voltage and Current Specification 2.6.1 Absolute Maximum and Minimum Ratings Table 3 specifies absolute maximum and minimum ratings only and lie outside the functional limits of the processor. Within functional operation limits, functionality and long-term reliability can be expected. At conditions outside functional operation condition limits, but within absolute maximum and minimum ratings, neither functionality nor long-term reliability can be expected.
Electrical Specifications 2.6.2 DC Voltage and Current Specification Table 4. Voltage and Current Specifications Symbol Parameter VID Range VID Processor Number (2 MB Cache): Core VCC 3.06 GHz E6500 2.93 GHz E6300 2.80 GHz E5200 2.50 GHz E5300 2.66 GHz E5400 2.70 GHz E5500 2.80 GHz VCC_BOOT Default VCC voltage for initial power up VCCPLL PLL VCC ICC VTT VTT_OUT_LEFT and VTT_OUT_RIGHT ICC ITT Typ Max Unit Notes2, 10 0.8500 — 1.
Electrical Specifications 3. 4. 5. 6. 7. 8. 9. 10. Table 5. These voltages are targets only. A variable voltage source should exist on systems in the event that a different voltage is required. See Section 2.3 and Table 2 for more information. The voltage specification requirements are measured across VCC_SENSE and VSS_SENSE lands at the socket with a 100 MHz bandwidth oscilloscope, 1.5 pF maximum probe capacitance, and 1 M minimum impedance.
Electrical Specifications Figure 1. Processor VCC Static and Transient Tolerance Icc [A] 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 VID - 0.000 VID - 0.013 VID - 0.025 Vcc Maximum VID - 0.038 VID - 0.050 VID - 0.063 Vcc [V] VID - 0.075 VID - 0.088 Vcc Typical VID - 0.100 VID - 0.113 Vcc Minimum VID - 0.125 VID - 0.138 VID - 0.150 VID - 0.163 VID - 0.175 VID - 0.188 NOTES: 1. 2. 3. 2.6.
Electrical Specifications Figure 2. VCC Overshoot Example Waveform Example Overshoot Waveform VOS Voltage [V] VID + 0.050 VID - 0.000 TOS 0 5 10 15 20 25 Time [us] TOS: Overshoot time above VID VOS: Overshoot above VID NOTES: 1. VOS is measured overshoot voltage. 2. TOS is measured time duration above VID. 2.6.4 Die Voltage Validation Overshoot events on processor must meet the specifications in Table 6 when measured across the VCC_SENSE and VSS_SENSE lands.
Electrical Specifications 2.7.1 FSB Signal Groups The front side bus signals have been combined into groups by buffer type. GTL+ input signals have differential input buffers, which use GTLREF[1:0] as a reference level. In this document, the term “GTL+ Input” refers to the GTL+ input group as well as the GTL+ I/O group when receiving. Similarly, “GTL+ Output” refers to the GTL+ output group as well as the GTL+ I/O group when driving.
Electrical Specifications . Table 8.
Electrical Specifications 2.7.3 Processor DC Specifications The processor DC specifications in this section are defined at the processor core (pads) unless otherwise stated. All specifications apply to all frequencies and cache sizes unless otherwise stated. Table 10. GTL+ Signal Group DC Specifications Symbol Parameter Min Max Unit Notes1 VIL Input Low Voltage -0.10 GTLREF – 0.10 V 2, 5 VIH Input High Voltage GTLREF + 0.10 VTT + 0.10 V 3, 4, 5 VOH Output High Voltage VTT – 0.
Electrical Specifications Table 12. CMOS Signal Group DC Specifications Symb ol Parameter Min Max Unit Notes1 VIL Input Low Voltage -0.10 VTT * 0.30 V 3, 6 VIH Input High Voltage VTT * 0.70 VTT + 0.10 V 4, 5, 6 VOL Output Low Voltage -0.10 VTT * 0.10 V 6 VOH Output High Voltage 0.90 * VTT VTT + 0.10 V 2, 5, 6 IOL Output Low Current VTT * 0.10 / 67 VTT * 0.10 / 27 A 6, 7 IOH Output Low Current VTT * 0.10 / 67 VTT * 0.
Electrical Specifications Table 13. PECI DC Electrical Limits Symbol Vin Definition and Conditions Input Voltage Range Vhysteresis Hysteresis Min Max Units -0.15 VTT V 0.1 * VTT — V Vn Negative-edge threshold voltage 0.275 * VTT 0.500 * VTT V Vp Positive-edge threshold voltage 0.550 * VTT 0.725 * VTT V Isource Isink High level output source (VOH = 0.75 * VTT) Low level output sink (VOL = 0.25 * VTT) -6.0 N/A mA 0.5 1.
Electrical Specifications Table 14. GTL+ Bus Voltage Definitions Parameter Min Typ Max Units Notes1 GTLREF_PU GTLREF pull up on Intel® 3 Series Chipset family boards 57.6 * 0.99 57.6 57.6 * 1.01 2 GTLREF_PD GTLREF pull down on Intel® 3 Series Chipset family boards 100 * 0.99 100 100 * 1.01 2 RTT Termination Resistance 45 50 55 3 COMP[3:0] COMP Resistance 49.40 49.90 50.40 4 COMP8 COMP Resistance 24.65 24.90 25.15 4 Symbol NOTES: 1.
Electrical Specifications Table 15. Core Frequency to FSB Multiplier Configuration Multiplication of System Core Frequency to FSB Frequency Core Frequency (200 MHz BCLK/ 800 MHz FSB) Core Frequency (266 MHz BCLK/ 1066 MHz FSB) Notes1, 2 1/6 1.20 GHz 1.60 GHz - 1/7 1.40 GHz 1.86 GHz - 1/7.5 1.5 GHz 2 GHz - 1/8 1.60 GHz 2.13 GHz - 1/8.5 1.70 GHz 2.26 GHz - 1/9 1.80 GHz 2.40 GHz - 1/9.5 1.90 GHz 2.53 GHz - 1/10 2 GHz 2.66 GHz - 1/10.5 2.1 GHz 2.80 GHz - 1/11 2.
Electrical Specifications Table 16. BSEL[2:0] Frequency Table for BCLK[1:0] BSEL2 2.8.3 BSEL1 BSEL0 FSB Frequency L L L 266 MHz L L H Reserved L H H Reserved L H L 200 MHz H H L Reserved H H H Reserved H L H Reserved H L L Reserved Phase Lock Loop (PLL) and Filter An on-die PLL filter solution will be implemented on the processor. The VCCPLL input is used for the PLL. Refer to Table 4 for DC specifications. 2.8.4 BCLK[1:0] Specifications Table 17.
Electrical Specifications Table 18. FSB Differential Clock Specifications (800 MHz FSB) Min Nom Max Unit Figure Notes1 BCLK[1:0] Frequency 198.980 — 200.020 MHz - 2 T1: BCLK[1:0] Period 4.99950 — 5.00050 ns 3 3 — — 150 ps 3 4 T5: BCLK[1:0] Rise and Fall Slew Rate 2.5 — 8 V/nS 3 5 T6: Slew Rate Matching N/A N/A 20 % T# Parameter T2: BCLK[1:0] Period Stability 6 NOTES: 1.
Electrical Specifications Figure 3. Differential Clock Waveform Tph Overshoot VH BCLK1 Rising Edge Ringback V CROSS (ABS) Threshold Region V CROSS (ABS) Ringback Margin Falling Edge Ringback BCLK0 VL Undershoot Tpl Tp Tp = T1: BCLK[1:0] period T2: BCLK[1:0] period stability (not shown) Tph = T3: BCLK[1:0] pulse high time Tpl = T4: BCLK[1:0] pulse low time T5: BCLK[1:0] rise time through the threshold region T6: BCLK[1:0] fall time through the threshold region Figure 4.
Electrical Specifications 32 Datasheet
Package Mechanical Specifications 3 Package Mechanical Specifications The processor is packaged in a Flip-Chip Land Grid Array (FC-LGA8) package that interfaces with the motherboard using an LGA775 socket. The package consists of a processor core mounted on a substrate land-carrier. An integrated heat spreader (IHS) is attached to the package substrate and core, and serves as the mating surface for processor component thermal solutions, such as a heatsink.
Package Mechanical Specifications Figure 6.
Package Mechanical Specifications Figure 7.
Package Mechanical Specifications Figure 8.
Package Mechanical Specifications 3.2 Processor Component Keep-Out Zones The processor may contain components on the substrate that define component keepout zone requirements. A thermal and mechanical solution design must not intrude into the required keep-out zones. Decoupling capacitors are typically mounted to either the top-side or land-side of the package substrate. See Figure 6 and Figure 7 for keep-out zones.
Package Mechanical Specifications 3.5 Package Insertion Specifications The processor can be inserted into and removed from a LGA775 socket 15 times. The socket should meet the LGA775 requirements detailed in the LGA775 Socket Mechanical Design Guide. 3.6 Processor Mass Specification The typical mass of the processor is 21.5 g [0.76 oz]. This mass [weight] includes all the components that are included in the package. 3.
Package Mechanical Specifications Figure 10. Intel® Pentium® Dual-Core Processor E6000 Series Top-Side Markings Example M INTEL ©'06 E6300 Intel® Pentium® Dual-Core SLGU9 [COO] 2.
Package Mechanical Specifications 3.9 Processor Land Coordinates Figure 11 shows the top view of the processor land coordinates. The coordinates are referred to throughout the document to identify processor lands. . Figure 11.
Land Listing and Signal Descriptions 4 Land Listing and Signal Descriptions This chapter provides the processor land assignment and signal descriptions. 4.1 Processor Land Assignments This section contains the land listings for the processor. The land-out footprint is shown in Figure 12 and Figure 13. These figures represent the land-out arranged by land number and they show the physical location of each signal on the package land array (top view).
Land Listing and Signal Descriptions Figure 12.
Land Listing and Signal Descriptions Figure 13.
Land Listing and Signal Descriptions Table 23. Land Name 44 Alphabetical Land Assignments Land Signal Buffer # Type Table 23.
Land Listing and Signal Descriptions Table 23. Land Name Datasheet Alphabetical Land Assignments Land Signal Buffer # Type Table 23.
Land Listing and Signal Descriptions Table 23. Land Name 46 Alphabetical Land Assignments Land Signal Buffer # Type Table 23.
Land Listing and Signal Descriptions Table 23. Land Name Datasheet Alphabetical Land Assignments Land Signal Buffer # Type Table 23.
Land Listing and Signal Descriptions Table 23. Land Name 48 Alphabetical Land Assignments Land Signal Buffer # Type Direction Table 23.
Land Listing and Signal Descriptions Table 23. Land Name Datasheet Alphabetical Land Assignments Land Signal Buffer # Type Direction Table 23.
Land Listing and Signal Descriptions Table 23. Land Name 50 Alphabetical Land Assignments Land Signal Buffer # Type Table 23.
Land Listing and Signal Descriptions Table 23. Land Name Datasheet Alphabetical Land Assignments Land Signal Buffer # Type Direction Table 23.
Land Listing and Signal Descriptions Table 23. Land Name 52 Alphabetical Land Assignments Land Signal Buffer # Type Direction Table 23.
Land Listing and Signal Descriptions Table 23. Land Name VSS Datasheet Alphabetical Land Assignments Land Signal Buffer # Type N6 Direction Table 23.
Land Listing and Signal Descriptions Table 24. Numerical Land Assignment Land # Land Name 54 Signal Buffer Type Table 24.
Land Listing and Signal Descriptions Table 24. Numerical Land Assignment Land # Land Name Datasheet Table 24.
Land Listing and Signal Descriptions Table 24. Numerical Land Assignment Land # Land Name 56 Table 24.
Land Listing and Signal Descriptions Table 24. Numerical Land Assignment Land # Land Name H29 Datasheet Signal Buffer Type Table 24.
Land Listing and Signal Descriptions Table 24. Numerical Land Assignment Land # Land Name 58 Signal Buffer Type Table 24.
Land Listing and Signal Descriptions Table 24. Numerical Land Assignment Land # Land Name Datasheet Signal Buffer Type Table 24.
Land Listing and Signal Descriptions Table 24. Numerical Land Assignment Land # Land Name 60 Signal Buffer Type Table 24.
Land Listing and Signal Descriptions Table 24. Numerical Land Assignment Land # Land Name Datasheet Signal Buffer Type Table 24.
Land Listing and Signal Descriptions Table 24. Numerical Land Assignment Land # Land Name 62 Signal Buffer Type Table 24.
Land Listing and Signal Descriptions Table 24. Numerical Land Assignment Land # Land Name AL16 Datasheet VSS Signal Buffer Type Table 24.
Land Listing and Signal Descriptions 4.2 Alphabetical Signals Reference Table 25. Signal Description (Sheet 1 of 10) Name A[35:3]# Type Input/ Output Description A[35:3]# (Address) define a 236-byte physical memory address space. In sub-phase 1 of the address phase, these signals transmit the address of a transaction. In sub-phase 2, these signals transmit transaction type information. These signals must connect the appropriate pins/lands of all agents on the processor FSB.
Land Listing and Signal Descriptions Table 25. Signal Description (Sheet 2 of 10) Name Type Description BPM[5:0]# (Breakpoint Monitor) are breakpoint and performance monitor signals. They are outputs from the processor which indicate the status of breakpoints and programmable counters used for monitoring processor performance. BPM[5:0]# should connect the appropriate pins/lands of all processor FSB agents. BPM[5:0]# Input/ Output BPM4# provides PRDY# (Probe Ready) functionality for the TAP port.
Land Listing and Signal Descriptions Table 25. Signal Description (Sheet 3 of 10) Name Type Description D[63:0]# (Data) are the data signals. These signals provide a 64bit data path between the processor FSB agents, and must connect the appropriate pins/lands on all such agents. The data driver asserts DRDY# to indicate a valid data transfer. D[63:0]# are quad-pumped signals and will, thus, be driven four times in a common clock period.
Land Listing and Signal Descriptions Table 25. Signal Description (Sheet 4 of 10) Name Type Description Input DEFER# is asserted by an agent to indicate that a transaction cannot be ensured in-order completion. Assertion of DEFER# is normally the responsibility of the addressed memory or input/ output agent. This signal must connect the appropriate pins/lands of all processor FSB agents.
Land Listing and Signal Descriptions Table 25. Signal Description (Sheet 5 of 10) Name Type Description FERR#/PBE# Output FERR#/PBE# (floating point error/pending break event) is a multiplexed signal and its meaning is qualified by STPCLK#. When STPCLK# is not asserted, FERR#/PBE# indicates a floating-point error and will be asserted when the processor detects an unmasked floating-point error.
Land Listing and Signal Descriptions Table 25. Signal Description (Sheet 6 of 10) Name ITP_CLK[1:0] LINT[1:0] Type Description Input ITP_CLK[1:0] are copies of BCLK that are used only in processor systems where no debug port is implemented on the system board. ITP_CLK[1:0] are used as BCLK[1:0] references for a debug port implemented on an interposer. If a debug port is implemented in the system, ITP_CLK[1:0] are no connects in the system. These are not processor signals.
Land Listing and Signal Descriptions Table 25. Signal Description (Sheet 7 of 10) Name PWRGOOD Type Input Description PWRGOOD (Power Good) is a processor input. The processor requires this signal to be a clean indication that the clocks and power supplies are stable and within their specifications. ‘Clean’ implies that the signal will remain low (capable of sinking leakage current), without glitches, from the time that the power supplies are turned on until they come within specification.
Land Listing and Signal Descriptions Table 25. Signal Description (Sheet 8 of 10) Name SLP# SMI# Type Description Input SLP# (Sleep), when asserted in Extended Stop Grant or Stop Grant state, causes the processor to enter the Sleep state. In the Sleep state, the processor stops providing internal clock signals to all units, leaving only the Phase-Locked Loop (PLL) still operating. Processors in this state will not recognize snoops or interrupts.
Land Listing and Signal Descriptions Table 25. Signal Description (Sheet 9 of 10) Name Type Description Output In the event of a catastrophic cooling failure, the processor will automatically shut down when the silicon has reached a temperature approximately 20 °C above the maximum TC. Assertion of THERMTRIP# (Thermal Trip) indicates the processor junction temperature has reached a level beyond where permanent silicon damage may occur.
Land Listing and Signal Descriptions Table 25. Signal Description (Sheet 10 of 10) Name Type Description VID[7:0] Output The VID (Voltage ID) signals are used to support automatic selection of power supply voltages (VCC). Refer to the Voltage Regulator Design Guide for more information. The voltage supply for these signals must be valid before the VR can supply VCC to the processor. Conversely, the VR output must be disabled until the voltage supply for the VID signals becomes valid.
Land Listing and Signal Descriptions 74 Datasheet
Thermal Specifications and Design Considerations 5 Thermal Specifications and Design Considerations 5.1 Processor Thermal Specifications The processor requires a thermal solution to maintain temperatures within the operating limits as set forth in Section 5.1.1. Any attempt to operate the processor outside these operating limits may result in permanent damage to the processor and potentially other components within the system.
Thermal Specifications and Design Considerations The case temperature is defined at the geometric top center of the processor. Analysis indicates that real applications are unlikely to cause the processor to consume maximum power dissipation for sustained time periods. Intel recommends that complete thermal solution designs target the Thermal Design Power (TDP) indicated in Table 26 instead of the maximum processor power consumption.
Thermal Specifications and Design Considerations Table 27. Figure 14. Processor Thermal Profile Power (W) Maximum Tc (°C) Power Maximum Tc (°C) Power Maximum Tc (°C) 0 44.9 24 55.7 48 66.5 2 45.8 26 56.6 50 67.4 4 46.7 28 57.5 52 68.3 6 47.6 30 58.4 54 69.2 8 48.5 32 59.3 56 70.1 10 49.4 34 60.2 58 71.0 12 50.3 36 61.1 60 71.9 14 51.2 38 62.0 62 72.8 16 52.1 40 62.9 64 73.7 18 53.0 42 63.8 65 74.1 20 53.9 44 64.7 22 54.8 46 65.
Thermal Specifications and Design Considerations 5.1.2 Thermal Metrology The maximum and minimum case temperatures (TC) for the processor is specified in Table 26. This temperature specification is meant to help ensure proper operation of the processor. Figure 15 illustrates where Intel recommends TC thermal measurements should be made. For detailed guidelines on temperature measurement methodology, refer to the appropriate Thermal and Mechanical Design Guidelines (see Section 1.2). Figure 15.
Thermal Specifications and Design Considerations periods of TCC activation is expected to be so minor that it would be immeasurable. An under-designed thermal solution that is not able to prevent excessive activation of the TCC in the anticipated ambient environment may cause a noticeable performance loss, and in some cases may result in a TC that exceeds the specified maximum temperature and may affect the long-term reliability of the processor.
Thermal Specifications and Design Considerations Figure 16. Thermal Monitor 2 Frequency and Voltage Ordering TTM2 Temperature fMAX fTM2 Frequency VID VIDTM2 VID PROCHOT# The PROCHOT# signal is asserted when a high temperature situation is detected, regardless of whether Thermal Monitor or Thermal Monitor 2 is enabled. Note that the Thermal Monitor 2 TCC cannot be activated using the on-demand mode. The Thermal Monitor TCC, however, can be activated through the use of the on-demand mode. 5.2.
Thermal Specifications and Design Considerations 5.2.4 PROCHOT# Signal An external signal, PROCHOT# (Processor Hot), is asserted when the processor core temperature has reached its maximum operating temperature. If the Thermal Monitor is enabled (note that the Thermal Monitor must be enabled for the processor to be operating within specification), the TCC will be active when PROCHOT# is asserted. The processor can be configured to generate an interrupt upon the assertion or deassertion of PROCHOT#.
Thermal Specifications and Design Considerations 5.3 Platform Environment Control Interface (PECI) 5.3.1 Introduction PECI offers an interface for thermal monitoring of Intel processor and chipset components. It uses a single wire, thus alleviating routing congestion issues. PECI uses CRC checking on the host side to ensure reliable transfers between the host and client devices. Also, data transfer speeds across the PECI interface are negotiable within a wide range (2 Kbps to 2 Mbps).
Thermal Specifications and Design Considerations 5.3.2 PECI Specifications 5.3.2.1 PECI Device Address The PECI register resides at address 30h. 5.3.2.2 PECI Command Support PECI command support is covered in detail in the Platform Environment Control Interface Specification. Refer to this document for details on supported PECI command function and codes. 5.3.2.
Thermal Specifications and Design Considerations 84 Datasheet
Features 6 Features 6.1 Power-On Configuration Options Several configuration options can be configured by hardware. The processor samples the hardware configuration at reset, on the active-to-inactive transition of RESET#. For specifications on these options, refer to Table 29. The sampled information configures the processor for subsequent operation. These configuration options cannot be changed except by another reset.
Features Figure 18.
Features The system can generate a STPCLK# while the processor is in the HALT powerdown state. When the system de-asserts the STPCLK# interrupt, the processor will return execution to the HALT state. While in HALT powerdown state, the processor will process bus snoops. 6.2.2.2 Extended HALT Powerdown State Extended HALT is a low power state entered when all processor cores have executed the HALT or MWAIT instructions and Extended HALT has been enabled using the BIOS.
Features 6.2.3.2 Extended Stop Grant State Extended Stop Grant is a low power state entered when the STPCLK# signal is asserted and Extended Stop Grant has been enabled using the BIOS. The processor will automatically transition to a lower frequency and voltage operating point before entering the Extended Stop Grant state. When entering the low power state, the processor will first switch to the lower bus ratio and then transition to the lower VID.
Features behavior.If RESET# is driven active while the processor is in the Sleep state, and held active as specified in the RESET# pin specification, then the processor will reset itself, ignoring the transition through the Stop-Grant state. If RESET# is driven active while the processor is in the Sleep state, the SLP# and STPCLK# signals should be de-asserted immediately after RESET# is asserted to ensure the processor correctly executes the Reset sequence.
Features In response to entering Deeper Sleep, the processor drives the VID code corresponding to the Deeper Sleep core voltage on the VID pins. Unlike typical Dynamic VID changes (where the steps are single VID steps), the processor will perform a VID jump on the order of 100 mV. To support the Deeper Sleep State the platform must use a VRD 11.1 compliant solution. 6.2.8 Enhanced Intel® SpeedStep® Technology The processor supports Enhanced Intel SpeedStep Technology.
Boxed Processor Specifications 7 Boxed Processor Specifications 7.1 Introduction The processor will also be offered as an Intel boxed processor. Intel boxed processors are intended for system integrators who build systems from baseboards and standard components. The boxed processor will be supplied with a cooling solution. This chapter documents baseboard and system requirements for the cooling solution that will be supplied with the boxed processor.
Boxed Processor Specifications 7.2 Mechanical Specifications 7.2.1 Boxed Processor Cooling Solution Dimensions This section documents the mechanical specifications of the boxed processor. The boxed processor will be shipped with an unattached fan heatsink. Figure 19 shows a mechanical representation of the boxed processor. Clearance is required around the fan heatsink to ensure unimpeded airflow for proper cooling.
Boxed Processor Specifications Figure 22. Overall View Space Requirements for the Boxed Processor 7.2.2 Boxed Processor Fan Heatsink Weight The boxed processor fan heatsink will not weigh more than 450 grams. See Chapter 5 and the appropriate Thermal and Mechanical Design Guidelines (see Section 1.2) for details on the processor weight and heatsink requirements. 7.2.
Boxed Processor Specifications The boxed processor's fan heatsink requires a constant +12 V supplied to pin 2 and does not support variable voltage control or 3-pin PWM control. The power header on the baseboard must be positioned to allow the fan heatsink power cable to reach it. The power header identification and location should be documented in the platform documentation, or on the system board itself. Figure 24 shows the location of the fan power connector relative to the processor socket.
Boxed Processor Specifications Figure 24. Baseboard Power Header Placement Relative to Processor Socket B R110 [4.33] C 7.4 Thermal Specifications This section describes the cooling requirements of the fan heatsink solution used by the boxed processor. 7.4.1 Boxed Processor Cooling Requirements The boxed processor may be directly cooled with a fan heatsink.
Boxed Processor Specifications Figure 25. Boxed Processor Fan Heatsink Airspace Keepout Requirements (side 1 view) Figure 26.
Boxed Processor Specifications 7.4.2 Variable Speed Fan If the boxed processor fan heatsink 4-pin connector is connected to a 3-pin motherboard header it will operate as follows: The boxed processor fan will operate at different speeds over a short range of internal chassis temperatures. This allows the processor fan to operate at a lower speed and noise level, while internal chassis temperatures are low.
Boxed Processor Specifications Table 31. Fan Heatsink Power and Signal Specifications Boxed Processor Fan Heatsink Set Point (°C) Boxed Processor Fan Speed Notes X 30 When the internal chassis temperature is below or equal to this set point, the fan operates at its lowest speed. Recommended maximum internal chassis temperature for nominal operating environment. 1 Y = 35 When the internal chassis temperature is at this point, the fan operates between its lowest and highest speeds.
Debug Tools Specifications 8 Debug Tools Specifications 8.1 Logic Analyzer Interface (LAI) Intel is working with two logic analyzer vendors to provide logic analyzer interfaces (LAIs) for use in debugging Intel Pentium® dual-core processor E5000 and E6000 series systems. Tektronix and Agilent should be contacted to get specific information about their logic analyzer interfaces. The following information is general in nature. Specific information must be obtained from the logic analyzer vendor.
Debug Tools Specifications 100 Datasheet
