Datasheet

Electrical Specifications
26 Datasheet
3. V
IL
is defined as the voltage range at a receiving agent that will be interpreted as a logical
low value.
4. V
IH
is defined as the voltage range at a receiving agent that will be interpreted as a logical
high value.
5. V
IH
and V
OH
may experience excursions above V
TT
. However, input signal drivers must
comply with the signal quality specifications in Chapter 3.
6. The V
TT
referred to in these specifications refers to instantaneous V
TT
.
7. I
OL
is measured at 0.10 * V
TT.
I
OH
is measured at 0.90 * V
TT.
8. Leakage to V
SS
with land held at V
TT
.
9. Leakage to V
TT
with land held at 300 mV.
2.8.3.1 Platform Environment Control Interface (PECI) DC Specifications
PECI is an Intel proprietary one-wire interface that provides a communication channel
between Intel processors, chipsets, and external thermal monitoring devices. The
Yorkfield processor contains Digital Thermal Sensors (DTS) distributed throughout die.
These sensors are implemented as analog-to-digital converters calibrated at the factory
for reasonable accuracy to provide a digital representation of relative processor
temperature. PECI provides an interface to relay the highest DTS temperature within a
die to external management devices for thermal/fan speed control. More detailed
information may be found in the Platform Environment Control Interface (PECI)
Specification.
.
2.8.3.2 GTL+ Front Side Bus Specifications
In most cases, termination resistors are not required as these are integrated into the
processor silicon. See Table 2-7 for details on which GTL+ signals do not include on-die
termination. Refer to the appropriate platform design guidelines for specific
implementation details.
Table 2-12. PECI DC Electrical Limits
Symbol Definition and Conditions Min Max Units Notes
1
NOTES:
1. V
TT
supplies the PECI interface. PECI behavior does not affect V
TT
min/max specifications. Please
refer to Table 2-3 for VTT specifications.
V
in
Input Voltage Range -0.15 V
TT
V
V
hysteresis
Hysteresis 0.1 * V
TT
-V
2
2. The leakage specification applies to powered devices on the PECI bus.
V
n
Negative-edge threshold voltage 0.275 * V
TT
0.500 * V
TT
V
V
p
Positive-edge threshold voltage 0.550 * V
TT
0.725 * V
TT
V
I
source
High level output source
(V
OH
= 0.75 * V
TT
)
-6.0 N/A mA
I
sink
Low level output sink
(V
OL
= 0.25 * V
TT
)
0.5 1.0 mA
I
leak+
High impedance state leakage to V
TT
N/A 50 µA
3
3. The input buffers use a Schmitt-triggered input design for improved noise immunity.
4. One node is counted for each client and one node for the system host. Extended trace lengths
might appear as additional nodes.
I
leak-
High impedance leakage to GND N/A 10 µA 2
C
bus
Bus capacitance per node -10pF4
V
noise
Signal noise immunity above 300 MHz 0.1 * V
TT
-V
p-p