Datasheet

Datasheet
23
Electrical Specifications
NOTES:
1. Refer to Section 4.2 for signal descriptions.
2. In processor systems where no debug port is implemented on the system board, these
signals are used to support a debug port interposer. In systems with the debug port
implemented on the system board, these signals are no connects.
3. The value of these signals during the active-to-inactive edge of RESET# defines the
processor configuration options. See Section 6.1 for details.
4. PROCHOT# signal type is open drain output and CMOS input.
Table 2-6. FSB Signal Groups
Signal Group Type Signals
1
GTL+ Common
Clock Input
Synchronous to
BCLK[1:0]
BPRI#, DEFER#, RESET#, RS[2:0]#, TRDY#
GTL+ Common
Clock I/O
Synchronous to
BCLK[1:0]
ADS#, BNR#, BPM[5:0]#, BPMb[3:0]#, BR0#
3
, DBSY#,
DRDY#, HIT#, HITM#, LOCK#
GTL+ Source
Synchronous I/O
Synchronous to
assoc. strobe
GTL+ Strobes
Synchronous to
BCLK[1:0]
ADSTB[1:0]#, DSTBP[3:0]#, DSTBN[3:0]#
CMOS
A20M#, DPSLP#, DPRSTP#, IGNNE#, INIT#, LINT0/
INTR, LINT1/NMI, SMI#
3
, STPCLK#, PWRGOOD, SLP#,
TCK, TDI, TDI_M, TMS, TRST#, BSEL[2:0], VID[7:0],
PSI#
Open Drain
Output
FERR#/PBE#, IERR#, THERMTRIP#, TDO, TDO_M
Open Drain
Input/Output
PROCHOT#
4
FSB Clock Clock BCLK[1:0], ITP_CLK[1:0]
2
Power/Other
VCC, VTT, VCCA, VCCIOPLL, VCCPLL, VSS, VSSA,
GTLREF[3:0], COMP[8,3:0], RESERVED,
TESTHI[13,11:10,7:0], VCC_SENSE,
VCC_MB_REGULATION, VSS_SENSE,
VSS_MB_REGULATION, DBR#
2
, VTT_OUT_LEFT,
VTT_OUT_RIGHT, VTT_SEL, FCx, PECI, MSID[1:0]
Signals Associated Strobe
REQ[4:0]#, A[16:3]#
3
ADSTB0#
A[35:17]#
3
ADSTB1#
D[15:0]#, DBI0# DSTBP0#, DSTBN0#
D[31:16]#, DBI1# DSTBP1#, DSTBN1#
D[47:32]#, DBI2# DSTBP2#, DSTBN2#
D[63:48]#, DBI3# DSTBP3#, DSTBN3#