Desktop 4th Generation Specification Sheet
Table Of Contents
- Contents
- Revision History
- 1.0 Introduction
- 2.0 Interfaces
- 3.0 Technologies
- 3.1 Intel® Virtualization Technology (Intel® VT)
- 3.2 Intel® Trusted Execution Technology (Intel® TXT)
- 3.3 Intel® Hyper-Threading Technology (Intel® HT Technology)
- 3.4 Intel® Turbo Boost Technology 2.0
- 3.5 Intel® Advanced Vector Extensions 2.0 (Intel® AVX2)
- 3.6 Intel® Advanced Encryption Standard New Instructions (Intel® AES-NI)
- 3.7 Intel® Transactional Synchronization Extensions - New Instructions (Intel® TSX-NI)
- 3.8 Intel® 64 Architecture x2APIC
- 3.9 Power Aware Interrupt Routing (PAIR)
- 3.10 Execute Disable Bit
- 3.11 Supervisor Mode Execution Protection (SMEP)
- 4.0 Power Management
- 4.1 Advanced Configuration and Power Interface (ACPI) States Supported
- 4.2 Processor Core Power Management
- 4.3 Integrated Memory Controller (IMC) Power Management
- 4.4 PCI Express* Power Management
- 4.5 Direct Media Interface (DMI) Power Management
- 4.6 Graphics Power Management
- 5.0 Thermal Management
- 5.1 Desktop Processor Thermal Profiles
- 5.2 Thermal Metrology
- 5.3 Fan Speed Control Scheme with Digital Thermal Sensor (DTS) 1.1
- 5.4 Fan Speed Control Scheme with Digital Thermal Sensor (DTS) 2.0
- 5.5 Processor Temperature
- 5.6 Adaptive Thermal Monitor
- 5.7 THERMTRIP# Signal
- 5.8 Digital Thermal Sensor
- 5.9 Intel® Turbo Boost Technology Thermal Considerations
- 6.0 Signal Description
- 6.1 System Memory Interface Signals
- 6.2 Memory Reference and Compensation Signals
- 6.3 Reset and Miscellaneous Signals
- 6.4 PCI Express*-Based Interface Signals
- 6.5 Display Interface Signals
- 6.6 Direct Media Interface (DMI)
- 6.7 Phase Locked Loop (PLL) Signals
- 6.8 Testability Signals
- 6.9 Error and Thermal Protection Signals
- 6.10 Power Sequencing Signals
- 6.11 Processor Power Signals
- 6.12 Sense Signals
- 6.13 Ground and Non-Critical to Function (NCTF) Signals
- 6.14 Processor Internal Pull-Up / Pull-Down Terminations
- 7.0 Electrical Specifications
- 8.0 Package Mechanical Specifications
- 9.0 Processor Ball and Signal Information
The Ψ
CA
point at DTS = -1 defines the minimum Ψ
CA
required at TDP considering the
worst case system design T
AMBIENT
design point:
Ψ
CA
= (T
CASE-MAX
– T
AMBIENT-TARGET
) / TDP
For example, for a 95 W TDP part, the T
case
maximum is 72.6 °C and at a worst case
design point of 40 °C local ambient this will result in:
Ψ
CA
= (72.6 – 40) / 95 = 0.34 °C/W
Similarly for a system with a design target of 45 °C ambient, the Ψ
CA
at DTS = -1
needed will be 0.29 °C/W.
The second point defines the thermal solution performance (Ψ
CA
) at T
CONTROL
. The
following table lists the required Ψ
CA
for the various TDP processors.
These two points define the operational limits for the processor for DTS 1.1
implementation. At T
CONTROL
the fan speed must be programmed such that the
resulting Ψ
CA
is better than or equivalent to the required Ψ
CA
listed in the following
table. Similarly, the fan speed should be set at DTS = -1 such that the thermal
solution performance is better than or equivalent to the Ψ
CA
requirements at T
AMBIENT-
MAX
. The fan speed controller must linearly ramp the fan speed from processor DTS =
T
CONTROL
to processor DTS = -1.
Figure 20. Digital Thermal Sensor (DTS) 1.1 Definition Points
Processor—Thermal Management
Desktop 4th Generation Intel
®
Core
™
Processor Family, Desktop Intel
®
Pentium
®
Processor Family, and Desktop Intel
®
Celeron
®
Processor Family
Datasheet – Volume 1 of 2 December 2013
72 Order No.: 328897-004