Instructions

The selected files are created and can be accessed from the output file folder as
specified in the output directory path. After the instantiation code is added to the file,
the oscena input must be made as a wire and assigned as a logic value of “1” to
enable the oscillator.
Implementation
You can implement these design examples with MAX II, MAX V, and Intel MAX 10
devices, all of which have the internal oscillator feature. Implementation involves
demonstration of the internal oscillator function by assigning the oscillator output to a
counter and driving the general purpose I/O (GPIO) pins on MAX II, MAX V, and Intel
MAX 10 devices.
Design Example 1: Targeting a MDN-82 Demo Board (MAX II Devices)
Design Example 1 is made to drive the LEDs to create a scrolling effect, thereby
demonstrating the internal oscillator using the MDN-82 demo board.
Table 3. EPM240G Pin Assignments for Design Example 1 Using the MDN-82 Demo
Board
EPM240G Pin Assignments
Signal Pin Signal Pin
d2
Pin 69
d3
Pin 40
d5
Pin 71
d6
Pin 75
d8
Pin 73
d10
Pin 73
d11
Pin 75
d12
Pin 71
d4_1
Pin 85
d4_2
Pin 69
d7_1
Pin 87
d7_2
Pin 88
d9_1
Pin 89
d9_2
Pin 90
sw9
Pin 82 — —
Assign the unused pins As input tri-stated in the Intel Quartus Prime software.
To demonstrate this design on the MDN-B2 demo board, follow these steps:
1. Turn on the power to the demo board (using slide switch SW1).
2. Download the design onto the MAX II CPLD through the JTAG header JP5 on the
demo board and a conventional programming cable (Intel FPGA Parallel Port Cable
or Intel FPGA Download Cable). Keep SW4 on the demo board pressed before and
during the start of the programming process. After it completes, turn off the
power and remove the JTAG connector.
3. Observe the scrolling LED sequence on the red LEDs and the bi-color LEDs.
Pressing SW9 on the demo board disables the internal oscillator and the scrolling
LEDs will freeze at their current positions.
Using the Internal Oscillator IP Core
683653 | 2017.11.06
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AN 496: Using the Internal Oscillator IP Core
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