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AN 496: Using the Internal Oscillator

IP Core

Online Version

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AN-496

ID: 683653

Version: 2017.11.06

Summary of content (8 pages)

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AN 496: Using the Internal Oscillator IP Core ID: 683653 Online Version Send Feedback AN-496 Version: 2017.11.
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Contents Contents Using the Internal Oscillator IP Core.................................................................................. 3 Internal Oscillators....................................................................................................... 3 Using the Internal Oscillator in MAX II and MAX V Devices................................................. 6 Using the Internal Oscillator in All Supported Devices (except MAX II and MAX V devices)......6 Implementation..........................
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683653 | 2017.11.06 Send Feedback Using the Internal Oscillator IP Core The supported Intel® devices offer a unique internal oscillator feature. As shown in the design examples described in this application note, internal oscillators make an excellent choice to implement designs that require clocking, thereby saving on-board space and costs associated with external clocking circuitry. Related Information • Design Example for MAX® II Provides the MAX® II design files for this application note (AN 496).
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Using the Internal Oscillator IP Core 683653 | 2017.11.06 Devices Cyclone® III Output Clock from Internal Oscillator (4) (MHz) 80 (max) Cyclone IV 80 (max) Cyclone V 100 (max) Intel Cyclone 10 GX 100 (max) Intel Cyclone 10 LP 80 (max) Arria® II GX 100 (max) Arria V 100 (max) Intel Arria 10 100 (max) Stratix® V 100 (max) Intel Stratix 10 170 – 230 (1) The output port for internal oscillator IP core is osc in MAX II and MAX V devices, and clkout in all other supported devices.
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Using the Internal Oscillator IP Core 683653 | 2017.11.06 Figure 1. Internal Oscillator as Part of the UFM for MAX II and MAX V Devices UFM Block PROGRAM RPT_BUSY Program Erase Control ERASE osc oscena BUSY 4 osc UFM Sector 1 ARCLK 9 UFM Sector 0 Address Register 16 16 ARSHFT ARDin DRDin Data Register DRDout DRCLK DRSHFT The internal oscillator is part of the Program Erase Control block, which controls the programming and erasing of the UFM.
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Using the Internal Oscillator IP Core 683653 | 2017.11.06 Using the Internal Oscillator in MAX II and MAX V Devices The internal oscillator has a single input, oscena, and a single output, osc. To activate the internal oscillator, use oscena. When activated, a clock with the frequency is made available at the output. If oscena is driven low, the output of the internal oscillator is a constant high. To instantiate the internal oscillator, follow these steps: 1.
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Using the Internal Oscillator IP Core 683653 | 2017.11.06 The selected files are created and can be accessed from the output file folder as specified in the output directory path. After the instantiation code is added to the file, the oscena input must be made as a wire and assigned as a logic value of “1” to enable the oscillator. Implementation You can implement these design examples with MAX II, MAX V, and Intel MAX 10 devices, all of which have the internal oscillator feature.
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Using the Internal Oscillator IP Core 683653 | 2017.11.06 Design Example 2: Targeting a MAX V Device Development Kit In Design Example 2, the oscillator output frequency is divided by 221 before clocking a 2-bit counter. The output of this 2-bit counter is used to drive the LEDs, thereby demonstrating the internal oscillator on the MAX V device development kit. Table 4.