Datasheet

Electrical Specifications
Datasheet 43
Table 11. AGTL+/CMOS Signal Group DC Specifications
Symbol Parameter Min. Typ. Max. Unit Notes
1
V
CCP
I/O Voltage 1.00 1.05 1.10 V 12
V
CCPC6
I/O Voltage for C6 1.00 1.05 1.10 V 12
GTLREF GTL Reference Voltage 2/3 V
CCP
V 6
CMREF CMOS Reference Voltage 1/2 V
CCP
V 6
R
COMP
Compensation Resistor 27.23 27.5 27.78 10
R
ODT
Termination Resistor 55 11
V
IH
Input High Voltage
GTLREF+0.10
or
CMREF+0.10
V
CCP
V
CCP
+0.10 V 3, 6
V
IL
Input Low Voltage -0.10 0
GTLREF0.10
or
CMREF0.10
V 2, 4
V
OH
Output High Voltage V
CCP
0.10 V
CCP
V
CCP
V 6
R
TT
Termination Resistance
46 [SS]
46 [CC]
55
61 [SS]
64 [CC]
7, 13
R
ON
(GTL
mode)
GTL Buffer on Resistance 21 25 29 5
R
ON
(CMOS
mode)
CMOS Buffer on Resistance
42 [SS]
42 [CC]
50
55 [SS]
58 [CC]
5, 13
I
LI
Input Leakage Current ±100 µA 8
Cpad Pad Capacitance 1.8 2.1 2.75 pF 9
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all processor
frequencies.
2. V
IL
is defined as the maximum voltage level at a receiving agent that will be
interpreted as a logical low value.
3. V
IH
is defined as the minimum voltage level at a receiving agent that will be interpreted
as a logical high value.
4. V
IH
and V
OH
may experience excursions above V
CCP
. However, input signal drivers must
comply with the signal quality specifications.
5. This is the pull-down driver resistance. Measured at 0.31*V
CCP
. R
ON
(minimum) =
0.4*R
TT
, R
ON
(typical) = 0.455*R
TT
, R
ON
(maximum) = 0.51*R
TT
. R
TT
typical value of
55 is used for R
ON
typical/minimum/maximum calculations.
6. GTLREF and CMREF should be generated from V
CCP
with a 1% tolerance resistor
divider. The V
CCP
referred to in these specifications is the instantaneous V
CCP
.
7. R
TT
is the on-die termination resistance measured at V
OL
of the AGTL+ output driver.
Measured at 0.31*V
CCP
. R
TT
is connected to V
CCP
on die.
8. Specified with on die R
TT
and R
ON
are turned off. Vin between 0 and V
CCP
.
9. Cpad includes die capacitance only. No package parasitics are included.
10. There is an external resistor on the comp0 and comp2 pins.
11. On die termination resistance, measured at 0.33*V
CCP
.
12. V
CCP
=V
CCP
C6 during normal operation. When in C6 state, V
CCP
=0 V while
V
CCP
C6=1.05 V.
13. SS: source synchronous pins such as quad-pumped data bus and double-pumped
address bus which require a clock strobe. CC: Common clock pins.