Datasheet

Electrical Specifications
36 Datasheet
Symbol Parameter Min. Typ. Max. Unit Notes
11
I
CCA
I
CC
for V
CCA
Supply — — 130 mA
I
CCP
+ I
CCPC6
I
CCP
+ I
CCPC6
before V
CC
Stable — — 2.5 A 8
I
CCP
+ I
CCPC6
I
CCP
+ I
CCPC6
after V
CC
Stable — — 1.5 A 9
NOTES:
1. Each processor is programmed with a maximum valid voltage identification value
(VID), which is set at manufacturing and cannot be altered. Individual maximum VID
values are calibrated during manufacturing such that two processors at the same
frequency may have different settings within the VID range. Note that this differs from
the VID employed by the processor during a power management event (Thermal
Monitor 2, Enhanced Intel SpeedStep technology, or Enhanced Halt State). Typical
AVID range is 0.75 V to 1.1 V.
2. The voltage specifications are assumed to be measured across VCC_SENSE and
VSS_SENSE pins at the socket with a 100-MHz bandwidth oscilloscope, 1.5-pF
maximum probe capacitance, and 1-MΩ minimum impedance. The maximum length of
ground wire on the probe should be less than 5 mm. Ensure external noise from the
system is not coupled in the scope probe.
3. Specified at 90°C T
J
.
4. Specified at the nominal V
CC
.
5. Measured at the bulk capacitors on the motherboard.
6. V
CC,BOOT
tolerance is shown in Figure 6 and Figure 7.
7. Based on simulations and averaged over the duration of any change in current.
Specified by design/characterization at nominal V
CC
. Not 100% tested.
8. This is a power-up peak current specification, which is applicable when V
CCP
is high and
V
CC_CORE
is low.
9. This is a steady-state I
CC
current specification, which is applicable when both V
CCP
and
V
CC_CORE
are high.
10. The V
CC
maximum supported by the process is 1.1 V but the parameter can change
(burn in voltage is higher).
11. Unless otherwise noted, all specifications in this table are based on estimates and
simulations or empirical data. These specifications will be updated with characterized
data from silicon measurements at a later date.
12. V
CCP
may be turned off during C6 power state— V
CCPC6
must always be powered on to
1.05 V -5/+10% on all power states.
13. The V
CC
power supply needs to be set to 0.3V during C6 power state.
14. V
CCP
(voltage rail which is turned off in C6, with SPLIT VTT Enabled) should ramp to
1.05 V while exiting C6 (Deep Power Down Technology State) at least 5µs before
V
CC_CORE
ramps to LFM VID. In addition, V
CCPC6
rail should remain at 1.05 -5/+10%
during V
CCP
ramp coming out of C6.