Datasheet
Electrical Specifications
32 Datasheet
Implementation of a source synchronous data bus determines the need to specify two
sets of timing parameters. One set is for common clock signals which are dependent
upon the rising edge of BCLK0 (ADS#, HIT#, HITM#, and so on.) and the second set
is for the source synchronous signals which are relative to their respective strobe lines
(data and address) as well as the rising edge of BCLK0. Asynchronous signals are still
present (A20M#, IGNNE#, and so on.) and can become active at any time during the
clock cycle. Table 5 identifies which signals are common clock, source synchronous,
and asynchronous.
Table 5. FSB Pin Groups
Signal Group Type Signals1
AGTL+ Common
Clock Input
Synchronous
to BCLK[1:0]
BPRI#, DEFER#, PREQ#4, RESET#, RS[2:0]#,
TRDY#, DPWR#
AGTL+ Common
Clock I/O
Synchronous
to BCLK[1:0]
ADS#, BNR#, BPM[3:0]#, BR0#, DBSY#, DRDY#,
HIT#, HITM#, LOCK#, PRDY#
CMOS Source
Synchronous I/O
Synchronous
to assoc.
strobe
Signals Associated Strobe
REQ[4:0]#, A[16:3]# ADSTB0#
A[31:17]# ADSTB1#
D[15:0]# DSTBP0#, DSTBN0#
D[31:16]# DSTBP1#, DSTBN1#
D[47:32]# DSTBP2#, DSTBN2#
D[63:48]# DSTBP3#, DSTBN3#
Strobes always use AGTL signaling—data pins are
CMOS only.
AGTL+ Strobes Synchronous
to BCLK[1:0]
ADSTB[1:0]#, DSTBP[3:0]#, DSTBN[3:0]#
CMOS Input Asynchronous DPRSTP#, DPSLP#, IGNNE#, INIT#, LINT0/INTR,
LINT1/ NMI, PWRGOOD, SMI#, SLP#, STPCLK#
Open Drain Output Asynchronous FERR#, THERMTRIP#, IERR#
Open Drain I/O Asynchronous PROCHOT#3
CMOS Output Asynchronous VID[6:0], BSEL[2:0]
CMOS Input Synchronous
to TCK
TCK, TDI, TMS, TRST#
Open Drain Output Synchronous
to TCK
TDO
FSB Clock Clock BCLK[1:0]
Power/Other COMP[3:0], HFPLL, CMREF, GTLREF, /DCLK, /ADK,
THERMDA, THERMDC, VCC, VCCA, VCCP,
VCC_SENSE, VSS, VSS_SENSE, VCCFUSE, VCCPC6
NOTES:
1. Refer to Chapter
4 for signal descriptions and termination requirements.
2. In processor systems where there is no debug port implemented on the system board,
these signals are used to support a debug port interposer. In systems with the debug
port implemented on the system board, these signals are no connects.
3. PROCHOT# signal type is open drain output and CMOS input.
4. On die termination differs from other AGTL+ signals.