Intel® Atom™ Processor Z5xx∆ Series Datasheet — For the Intel® Atom™ Processor Z560∆, Z550∆, Z540∆, Z530∆, Z520∆, Z515∆, Z510∆, and Z500∆ on 45 nm Process Technology June 2010 Document Number: 319535-003US
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Contents 1 Introduction ...................................................................................................... 7 1.1 1.2 1.3 1.4 2 Low Power Features .......................................................................................... 13 2.1 2.2 2.3 2.4 2.5 2.6 3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 4.2 4.3 Package Mechanical Specifications ........................................................... 47 4.1.1 Processor Package Weight .......................................
5.1.4 5.1.5 Out of Specification Detection .................................................... 72 PROCHOT# Signal Pin ............................................................... 72 Figures Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure 1. Thread Low-Power States ..................................................................... 14 2. Package Low-Power States ................................................................... 14 3. Deep Power Down Technology Entry Sequence .
Revision History Document Number Revision Number 319535 001 319535 002 Description Revision Date • Initial release April 2008 ® • Updated information about Intel Z515 and Z550. Atom processors March 2009 • Added Intel® Atom processor Z550 specifications to Table 7 • Changed VccBoot value to VccLFM in Table 7 and Table 8. • Added new Table 9, Voltage and Current Specifications for Intel® Atom processor Z515. • Removed EMTTM references as it is not a supported feature.
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Introduction 1 Introduction The Intel® Atom™ processor Z5xx series is built on a new 45-nanometer Hi-k low power micro-architecture and 45 nm process technology—the first generation of lowpower IA-32 micro-architecture specially designed for the new class of Mobile Internet Devices (MIDs). The Intel Atom processor Z5xx series supports the Intel® System Controller Hub (Intel® SCH), a single-chip component designed for low-power operation. 1.
Introduction • Execute Disable Bit support for enhanced security • Intel® Burst Performance Technology (Intel® BPT) (Intel Atom processor Z515 only) 8 Datasheet
Introduction 1.3 Terminology Term Datasheet Definition # A “#” symbol after a signal name refers to an active low signal, indicating a signal is in the active state when driven to a low level. For example, when RESET# is low, a reset has been requested. Conversely, when NMI is high, a non-maskable interrupt has occurred.
Introduction Term 10 Definition VCC,BOOT Default VCC Voltage for Initial Power Up VCCP AGTL+ Termination Voltage VCCPC6 AGTL+ Termination Voltage VCCA PLL Supply voltage VCCDPPWDN VCC at Deep Power Down Technology (C6) VCCDPRSLP VCC at Deeper Sleep (C4) VCCF Fuse Power Supply ICCDES ICCDES for Intel Atom processors Z5xx Series Recommended Design Target power delivery (Estimated) ICC ICC for Intel Atom processors Z5xx Series is the number that can be use as a reflection on a battery life
Introduction 1.4 References Material and concepts available in the following documents may be beneficial when reading this document. Table 1. References Document Document Number Intel® System Controller Hub (Intel® SCH) Datasheet http://www.intel.com/desi gn/chipsets/embedded/S CHUS15W/techdocs.htm Intel® Atom™ Processor Z5xx Series Specification Update http://www.intel.com/desi gn/chipsets/embedded/S CHUS15W/techdocs.
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Low Power Features 2 Low Power Features 2.1 Clock Control and Low-Power States The processor supports low power states at the thread level and the core/package level. Thread states (TCx) loosely correspond to ACPI processor power states (Cx). A thread may independently enter the TC1/AutoHALT, TC1/MWAIT, TC2, TC4, or TC6 low power states, but this does not always cause a power state transition.
Low Power Features Figure 1.
Low Power Features Table 2.
Low Power Features 2.1.1.1.2 C1/MWAIT Powerdown State C1/MWAIT is a low-power state entered when one thread executes the MWAIT(C1) instruction while the other thread is in the TC1 or greater thread state. Processor behavior in the MWAIT state is identical to the AutoHALT state except that Monitor events can cause the processor to return to the C0 state.
Low Power Features 2.1.1.2.2 Stop-Grant Snoop State The processor responds to snoop or interrupt transactions on the FSB while in StopGrant state by entering the Stop-Grant Snoop state. The processor will stay in this state until the snoop on the FSB has been serviced (whether by the processor or another agent on the FSB) or the interrupt has been latched. The processor returns to the Stop-Grant state once the snoop has been serviced or the interrupt has been latched. 2.1.1.
Low Power Features 2.1.1.3.2 Deep Sleep State The Deep Sleep state is entered through assertion of the DPSLP# pin while in the Sleep state and is also only a transition state for the Intel Atom processor Z5xx series. BCLK may be stopped during the Deep Sleep state for additional platform level power savings.
Low Power Features 2.1.1.3.4 Intel® Atom™ Processor Z5xx Series C5 As mentioned previously in this document, each C-state has latency and transitory power costs associated with entering/exiting idle states. When the processor is interrupted, it must awake to service requests. If these requests occur at a high frequency, it is possible that more power will be consumed entering/exiting the states than will be saved.
Low Power Features 2.1.1.4.1 Intel® Deep Power Down Technology State (Package C6 State) When both threads have entered the C6 state and the L2 cache has been shrunk down to zero ways, the processor will enter the Package Deep Power Down Technology state. To do so, the processor saves its architectural states in the on-die SRAM that resides in the VCCP domain. At this point, the core VCC will be dropped to the lowest core voltage (closer to 0.3 V). The processor is now in an extremely low-power state.
Low Power Features Figure 5 shows the relative exit latencies of the package sleep states discussed above. Note: Figure 5 uses pre-silicon estimates. Silicon based data will be provided in a future revision of this document. Figure 5.
Low Power Features 2.2 Dynamic Cache Sizing Dynamic Cache Sizing allows the processor to flush and disable a programmable number of L2 cache ways upon each Deeper Sleep entry under the following conditions: • The C0 timer that tracks continuous residency in the Normal package state has not expired. This timer is cleared during the first entry into Deeper Sleep to allow consecutive Deeper Sleep entries to shrink the L2 cache as needed.
Low Power Features 2.3 Enhanced Intel SpeedStep® Technology The processor features Enhanced Intel SpeedStep® Technology. The following are the key features of Enhanced Intel SpeedStep® Technology: • Multiple voltage and frequency operating points providing optimal performance at the lowest power.
Low Power Features 2.4 Enhanced Low-Power States Enhanced low-power states (C1E, C2E, and C4E) optimize for power by forcibly reducing the performance state of the processor when it enters a package low-power state. Instead of directly transitioning into the package low-power state, the enhanced package low-power state first reduces the performance state of the processor by performing an Enhanced Intel SpeedStep Technology transition down to the lowest operating point.
Low Power Features 2.5 FSB Low Power Enhancements The processor incorporates FSB low power enhancements: • BPRI# control for address and control input buffers • Dynamic Bus Parking • Dynamic On Die Termination disabling • Low VCCP (I/O termination voltage) • CMOS Front Side Bus The processor incorporates the DPWR# signal that controls the data bus input buffers on the processor.
Low Power Features 2.6 Intel® Burst Performance Technology (Intel® BPT) The processor supports ACPI Performance States (P-States). The P-state referred to as P0 will be a request for Intel® Burst Performance Technology (Intel® BPT). Intel BPT opportunistically, and automatically, allows the processor to run faster than the marked frequency if the part is operating within the thermal design limits of the platform. Intel BPT mode provides more performance on demand without impacting or raising MID thermals.
Electrical Specifications 3 Electrical Specifications This chapter contains signal group descriptions, absolute maximum ratings, voltage identification, and power sequencing. The chapter also includes DC specifications. 3.1 FSB, GTLREF, and CMREF The processor supports two kinds of signalling protocol: Complementary Metal Oxide Semiconductor (CMOS), and Advanced Gunning Transceiver Logic (AGTL+).
Electrical Specifications 3.3 Decoupling Guidelines Due to its large number of transistors and high internal clock speeds, the processor is capable of generating large average current swings between low and full power states. This may cause voltages on power planes to sag below their minimum values if bulk decoupling is not adequate.
Electrical Specifications Table 3. Voltage Identification Definition Datasheet VID6 VID5 VID4 VID3 VID2 VID1 VID0 VCC (V) 0 0 1 1 0 0 0 1.2000 0 0 1 1 0 0 1 1.1875 0 0 1 1 0 1 0 1.1750 0 0 1 1 0 1 1 1.1625 0 0 1 1 1 0 0 1.1500 0 0 1 1 1 0 1 1.1375 0 0 1 1 1 1 0 1.1250 0 0 1 1 1 1 1 1.1125 0 1 0 0 0 0 0 1.1000 0 1 0 0 0 0 1 1.0875 0 1 0 0 0 1 0 1.0750 0 1 0 0 0 1 1 1.0625 0 1 0 0 1 0 0 1.
Electrical Specifications 30 VID6 VID5 VID4 VID3 VID2 VID1 VID0 VCC (V) 0 1 1 1 1 1 0 0.7250 0 1 1 1 1 1 1 0.7125 1 0 0 0 0 0 0 0.7000 1 0 0 0 0 0 1 0.6875 1 0 0 0 0 1 0 0.6750 1 0 0 0 0 1 1 0.6625 1 0 0 0 1 0 0 0.6500 1 0 0 0 1 0 1 0.6375 1 0 0 0 1 1 0 0.6250 1 0 0 0 1 1 1 0.6125 1 0 0 1 0 0 0 0.6000 1 0 0 1 0 0 1 0.5875 1 0 0 1 0 1 0 0.5750 1 0 0 1 0 1 1 0.5625 1 0 0 1 1 0 0 0.
Electrical Specifications 3.6 Catastrophic Thermal Protection The processor supports the THERMTRIP# signal for catastrophic thermal protection. An external thermal sensor should also be used to protect the processor and the system against excessive temperatures. Even with the activation of THERMTRIP#, which halts all processor internal clocks and activity, leakage current can be high enough such that the processor cannot be protected in all conditions without the removal of power to the processor.
Electrical Specifications Implementation of a source synchronous data bus determines the need to specify two sets of timing parameters. One set is for common clock signals which are dependent upon the rising edge of BCLK0 (ADS#, HIT#, HITM#, and so on.) and the second set is for the source synchronous signals which are relative to their respective strobe lines (data and address) as well as the rising edge of BCLK0. Asynchronous signals are still present (A20M#, IGNNE#, and so on.
Electrical Specifications 3.10 CMOS Asynchronous Signals CMOS input signals are shown in Table 5. Legacy output FERR#, IERR#, and other non- AGTL+ signals (THERMTRIP# and PROCHOT#) use Open Drain output buffers. These signals do not have setup or hold time specifications in relation to BCLK[1:0]. However, all of the CMOS signals are required to be asserted for more than 5 BCLKs for the processor to recognize them. See Section 3.12 for the DC specifications for the CMOS signal groups. 3.
Electrical Specifications Table 6. Processor Absolute Maximum Ratings Symbol Parameter Min. Max. Unit Notes1 TSTORAGE Processor Storage Temperature -40 85 °C 2, 3, 4 VCC, VCCP, VCCPC6 Any Processor Supply Voltage with Respect to VSS -0.3 1.10 V 5 VCCA PLL power supply -0.3 1.575 V VinAGTL+ AGTL+ Buffer DC Input Voltage with Respect to VSS -0.1 1.10 V VinAsynch_CMOS CMOS Buffer DC Input Voltage with Respect to VSS -0.1 1.10 V NOTES: 1.
Electrical Specifications Table 7. Voltage and Current Specifications for the Intel® Atom™ Processor Z560, Z550, Z540, Z530, Z520, and Z510 Symbol Parameter Min. Typ. Max. Unit 100.00 — 133.35 MHz Notes11 FSB Frequency BCLK Frequency VCCHFM VCC @ Highest Frequency Mode (HFM) AVID — 1.10 V 1, 2, 10 VCCLFM VCC @ Lowest Frequency Mode (LFM) 0.8 — AVID V 1, 2 VCC,BOOT Default VCC Voltage for Initial Power Up — VCCLFM — V 2, 6 VCCP AGTL+ Termination Voltage 1.00 1.05 1.
Electrical Specifications Symbol Parameter Min. Typ. Max. Unit Notes11 ICCA ICC for VCCA Supply — — 130 mA ICCP+ ICCPC6 ICCP + ICCPC6 before VCC Stable — — 2.5 A 8 ICCP+ ICCPC6 ICCP + ICCPC6 after VCC Stable — — 1.5 A 9 NOTES: 1. Each processor is programmed with a maximum valid voltage identification value (VID), which is set at manufacturing and cannot be altered.
Electrical Specifications Table 8. Voltage and Current Specifications for the Intel® Atom™ Processor Z500 Symbol Parameter Min. Typ. Max. Unit — 100.0 -— MHz Notes11 FSB Frequency BCLK Frequency VCCHFM VCC @ Highest Frequency Mode (HFM) AVID — 0.85 V 1, 2, 10 VCCLFM VCC @ Lowest Frequency Mode (LFM) 0.75 — AVID V 1, 2 VCC,BOOT Default VCC Voltage for Initial Power Up — VCCLFM — V 2, 6 VCCP AGTL+ Termination Voltage 1.00 1.05 1.
Electrical Specifications 6. 7. 8. 9. 10. 11. 12. 13. 14. VCC,BOOT tolerance is shown in Figure 6 and Figure 7. Based on simulations and averaged over the duration of any change in current. Specified by design/characterization at nominal VCC. Not 100% tested. This is a power-up peak current specification, which is applicable when VCCP is high and VCC_CORE is low. This is a steady-state ICC current specification, which is applicable when both VCCP and VCC_CORE are high.
Electrical Specifications Parameter Min. Typ. Max. Unit Notes11 dICC/dt V Power Supply Current Slew Rate @ Processor Package Pin (Estimated) — — 2.5 A/µs 5, 7 ICCA ICCA for V Supply — — 130 mA ICCP+ ICCPC6 ICCP+ ICCPC6 before V Stable — — 2.5 A 8 ICCP+ ICCPC6 ICCP+ ICCPC6 after V Stable — — 1.5 A 9 Symbol NOTES: 1. Each processor is programmed with a maximum valid voltage identification value (VID), which is set at manufacturing and cannot be altered.
Electrical Specifications Figure 6. Active Vcc and Icc Loadline VCC (V) Slope = -5.7 mV/A at package VCC_SENSE, VSS_SENSE pins. Differential Remote Sense required. 10 mV = Ripple VCC Max[HFM][LFM] VCC, DC Max[HFM][LFM] VCC Nom[HFM][LFM] VCC, DC Min[HFM][LFM] VCC Min[HFM][LFM] ±VCC nom*1.5 % = VR ST Pt Error 1/ ICC (A) 0 ICC max[HFM][LFM] Note 1/ VCC Set Point Error Tolerance is per below: Tolerance -------------------------------±1.5% ±11.
Electrical Specifications Figure 7. Deeper Sleep VCC and ICC Loadline VCC_CORE (V) Slope = -5.7 mV/A at package VCC_SENSE, VSS_SENSE pins. Differential Remote Sense required.
Electrical Specifications Table 10. FSB Differential BCLK Specifications Symbol Parameter Min. Typ. Max. Unit Figure Notes1 VIH Input High Voltage — — 1.15 V 7, 8 VIL Input Low Voltage — — -0.3 V 7, 8 0.3 — 0.55 V 2, 7, 9 VCROSS Crossing Voltage ∆VCROSS Range of Crossing Points — — 140 mV 2, 7, 5 VSWING Differential Output Swing 300 — — mV 6 Input Leakage Current -5 — +5 µA 3 Pad Capacitance 1.2 1.45 2.0 pF 4 ILI Cpad NOTES: 1.
Electrical Specifications Table 11. AGTL+/CMOS Signal Group DC Specifications Symbol VCCP VCCPC6 Min. Typ. Max. Unit Notes1 I/O Voltage 1.00 1.05 1.10 V 12 I/O Voltage for C6 1.00 1.05 1.10 V 12 Parameter GTLREF GTL Reference Voltage — 2/3 VCCP — V 6 CMREF CMOS Reference Voltage — 1/2 VCCP — V 6 27.23 27.5 27.78 Ω 10 — 55 — Ω 11 RCOMP Compensation Resistor RODT Termination Resistor VIH Input High Voltage GTLREF+0.10 or CMREF+0.10 VCCP VCCP+0.
Electrical Specifications Table 12. Legacy CMOS Signal Group DC Specifications Min. Typ. Max. Unit Notes1 I/O Voltage 1.00 1.05 1.10 V 8 VCCPC6 I/O Voltage for C6 1.00 1.05 1.10 V 8 VIH Input High Voltage 0.7*VCCP VCCP VCCP+0.1 V 2 VIL Input Low Voltage CMOS -0.10 0.00 0.3*VCCP V 2 VOH Output High Voltage 0.9*VCCP VCCP VCCP+0.1 V 2 VOL Output Low Voltage -0.10 0 0.1*VCCP V 2 IOH Output High Current 1.5 — 4.1 mA 4 IOL Output Low Current 1.5 — 4.
Electrical Specifications 3.13 AGTL+ FSB Specifications Termination resistors are not required for most AGTL+ signals, as these are integrated into the processor silicon. Valid high and low levels are determined by the input buffers which compare a signal’s voltage with a reference voltage called GTLREF (known as VREF in previous documentation). Table 11 lists the GTLREF and CMREF specifications.
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Package Mechanical Specifications and Pin Information 4 Package Mechanical Specifications and Pin Information This chapter describes the package specifications, pinout assignments, and signal descriptions. 4.1 Package Mechanical Specifications The processor will be available in 512 KB, 441 pins in FCBGA8 package. The package dimensions are shown in Figure 8. 4.1.1 Processor Package Weight The Intel Atom processor Z5xx series package weight is 0.475 g.
Package Mechanical Specifications and Pin Information Figure 8.
Package Mechanical Specifications and Pin Information 4.2 Processor Pinout Assignment Figure 9 and Figure 10 are graphic representations of the processor pinout assignments. Table 14 lists the pinout by signal name. Figure 9.
Package Mechanical Specifications and Pin Information Figure 10.
Package Mechanical Specifications and Pin Information Table 14.
Package Mechanical Specifications and Pin Information 52 Signal Name Ball # Signal Name Ball # Signal Name Ball # D[36]# AH9 DINV[1]# AE22 REQ[1]# D23 D[37]# AE10 DINV[2]# AE12 REQ[2]# E20 D[38]# AJ16 DINV[3]# Y5 REQ[3]# A24 D[39]# AF13 DPRSTP# G2 REQ[4]# B21 D[40]# AF7 DPSLP# G6 RESET# M5 D[41]# AF15 DPWR# V31 RS[0]# D27 D[42]# AH13 DRDY# W28 RS[1]# E28 D[43]# AJ14 DSTBN[0]# AA28 RS[2]# E26 D[44]# AJ12 DSTBN[1]# AF21 RSVD K29 D[45]# AH7 DSTBN[
Package Mechanical Specifications and Pin Information Datasheet Signal Name Ball # Signal Name Ball # Signal Name Ball # TEST4 U30 VCC R16 VCCP AA22 THERMTRIP# T1 VCC R18 VCCP AB7 THRMDA T5 VCC R20 VCCP AB9 THRMDC U4 VCC R22 VCCP AB11 TMS P1 VCC R24 VCCP AB13 TRDY# F25 VCC U6 VCCP AB15 TRST# J4 VCC U8 VCCP AB17 VCC L8 VCC U10 VCCP AB19 VCC L10 VCC U12 VCCP AB21 VCC L12 VCC U14 VCCP AB23 VCC L14 VCC U16 VCCP H11 VCC L16 VCC U18 VCC
Package Mechanical Specifications and Pin Information 54 Signal Name Ball # Signal Name Ball # Signal Name Ball # VCCPC6 H9 VSS AD21 VSS C16 VCCPC6 J8 VSS AD23 VSS C18 VCCPC6 M27 VSS AD25 VSS C20 VCC_SENSE W2 VSS AD29 VSS C22 VID[0] P5 VSS/NCTF AF1 VSS C24 VID[1] R4 VSS/NCTF AF31 VSS/NCTF C30 VID[2] N4 VSS/NCTF AG2 VSS/NCTF D1 VID[3] K5 VSS AG6 VSS/NCTF D31 VID[4] L4 VSS AG8 VSS F3 VID[5] R2 VSS AG10 VSS F9 VID[6] U2 VSS AG12 VSS F11
Package Mechanical Specifications and Pin Information Datasheet Signal Name Ball # Signal Name Ball # Signal Name Ball # VSS K9 VSS P11 VSS V11 VSS K11 VSS P13 VSS V13 VSS K13 VSS P15 VSS V15 VSS K15 VSS P17 VSS V17 VSS K17 VSS P19 VSS V19 VSS K19 VSS P21 VSS V21 VSS K21 VSS P23 VSS V23 VSS K23 VSS P25 VSS V25 VSS K25 VSS P27 VSS V29 VSS L6 VSS T3 VSS W6 VSS M3 VSS T7 VSS Y3 VSS M7 VSS T9 VSS Y7 VSS M9 VSS T11 VSS Y9 VSS
4.3 Signal Description Table 15. Signal Description Signal Name Type Description A[31:3]# (Address) defines a 232-byte physical memory address space. In subphase 1 (one) of the address phase, these pins transmit the address of a transaction. A[31:3]# A20M# I/O I In sub-phase 2, these pins transmit transaction type information. These signals must connect the appropriate pins of both agents on the processor FSB.
Package Mechanical Specifications and Pin Information Signal Name Type Description BPM[0]# O BPM[1]# I/O BPM[2]# O BPM[3]# I/O BPM[3:0]# (Breakpoint Monitor) are breakpoint and performance monitor signals. They are outputs from the processor which indicate the status of breakpoints and programmable counters used for monitoring processor performance. BPM[3:0]# should connect the appropriate pins of all FSB agents. This includes debug or performance monitoring tools.
Signal Name DBSY# DEFER# DINV[3:0]# Type Description I/O DBSY# (Data Bus Busy) is asserted by the agent responsible for driving data on the FSB to indicate that the data bus is in use. The data bus is released after DBSY# is de-asserted. This signal must connect the appropriate pins on both FSB agents. I DEFER# is asserted by an agent to indicate that a transaction cannot be guaranteed in-order completion.
Package Mechanical Specifications and Pin Information Signal Name FERR#/PBE# Type O Description FERR# (Floating-point Error) PBE# (Pending Break Event) is a multiplexed signal and its meaning is qualified with STPCLK#. When STPCLK# is not asserted, FERR#/PBE# indicates a floating point when the processor detects an unmasked floating-point error.
Signal Name INIT# Type I Description INIT# (Initialization), when asserted, resets integer registers inside the processor without affecting its internal caches or floating-point registers. The processor then begins execution at the power-on Reset vector configured during power-on configuration. The processor continues to handle snoop requests during INIT# assertion. INIT# is an asynchronous signal.
Package Mechanical Specifications and Pin Information Signal Name PWRGOOD Type I Description PWRGOOD (Power Good) is a processor input. The processor requires this signal to be a clean indication that the clocks and power supplies are stable and within their specifications. “Clean” implies that the signal will remain low (capable of sinking leakage current), without glitches, from the time that the power supplies are turned on until they come within specification.
Signal Name 62 Type Description STPCLK# I STPCLK# (Stop Clock), when asserted, causes the processor to enter a low power Stop-Grant state. The processor issues a StopGrant Acknowledge transaction, and stops providing internal clock signals to all processor core units except the FSB and APIC units. The processor continues to snoop bus transactions and service interrupts while in Stop-Grant state. When STPCLK# is de-asserted, the processor restarts its internal clock to all units and resumes execution.
Package Mechanical Specifications and Pin Information Signal Name VID[6:0] Type O Description VID[6:0] (Voltage ID) pins are used to support automatic selection of power supply voltages (VCC). Unlike some previous generations of processors, these are CMOS signals that are driven by the processor. The voltage supply for these pins must be valid before the VR can supply VCC to the processor. Conversely, the VR output must be disabled until the voltage supply for the VID pins becomes valid.
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Thermal Specifications and Design Considerations 5 Thermal Specifications and Design Considerations The processor requires a thermal solution to maintain temperatures within operating limits as set forth in Section 5.1. Any attempt to operate the processor outside these operating limits may result in permanent damage to the processor and potentially other components in the system. As processor technology changes, thermal management becomes increasingly crucial when building computer systems.
Table 16. Power Specifications for Intel® Atom™ Processors Z560, Z550, Z540, Z530, Z520, and Z510 Symbol Processor Number Z510 Z520 TDP Z530 Z540 Z550 Z560 Symbol Core Frequency and Voltage Thermal Design Power Unit Notes 2.0 W W @ 90°C 1.1 GHz and HFM VCC 0.6 GHZ and LFM VCC 1, 4 1.33 GHz and HFM VCC 0.8 GHZ and LFM VCC 2.0 W 2.2 W with HT enabled W 1.60 GHz and HFM VCC 0.8 GHZ and LFM VCC 2.0 W 2.2 W with HT enabled W 1.86 GHz and HFM VCC 0.8 GHZ and LFM VCC 2.4 W 2.
Thermal Specifications and Design Considerations Table 17. Power Specifications for Intel® Atom™ Processors Z515 and Z500 Symbol TDP Processor Number Z500/Z515 0.8 GHz and HFM VCC Z500/Z515 0.6 GHz and LFM VCC Symbol PAH, PSGNT PDPRSLP PDC6 TJ Core Frequency and Voltage Parameter Thermal Design Power 0.65 Min. Typ. Unit W Max. Unit Notes @ 90°C 1, 4, 6, 7 Notes @ 70°C Auto Halt, Stop Grant Power @ HFM VCC — — 0.6 W 2, 6, 7 @ LFM VCC — — 0.5 W Deeper Sleep Power — — 0.
5.1 Thermal Specifications The processor incorporates three methods of monitoring die temperature—Digital Thermal Sensor, Intel Thermal Monitor, and the Thermal Diode. The Intel Thermal Monitor (detailed in Section 5.1.2) must be used to determine when the maximum specified processor junction temperature has been reached. 5.1.1 Thermal Diode The processor incorporates an on-die PNP transistor whose base emitter junction is used as a thermal “diode”, with its collector shorted to ground.
Thermal Specifications and Design Considerations Table 18. Thermal Diode Interface Signal Name Pin/Ball Number Signal Description THERMDA T5 Thermal diode anode THERMDC U4 Thermal diode cathode Table 19. Thermal Diode Parameters Using Transistor Model Min. Typ. Max. Unit Note s Forward Bias Current 5 — 200 µA 1 IE Emitter Current 5 — 200 µA 1 nQ Transistor Ideality 0.997 1.001 1.015 2, 3, 4 0.25 — 0.65 2, 3 2.79 4.52 6.
5.1.2 Intel® Thermal Monitor The Intel Thermal Monitor helps control the processor temperature by activating the TCC (Thermal Control Circuit) when the processor silicon reaches its maximum operating temperature. The temperature at which the Intel Thermal Monitor activates the TCC is not user configurable. Bus traffic is snooped in the normal manner and interrupt requests are latched (and serviced during the time that the clocks are on) while the TCC is active.
Thermal Specifications and Design Considerations over TM2 is enabled in MSRs using BIOS and TM2 is not sufficient to cool the processor below the maximum operating temperature, then TM1 will also activate to help cool down the processor.
5.1.3 Digital Thermal Sensor The processor also contains an on die Digital Thermal Sensor (DTS) that is read using an MSR (no I/O interface). The processor has a unique digital thermal sensor that’s temperature is accessible using the processor MSRs.
Thermal Specifications and Design Considerations The processor implements a bidirectional PROCHOT# capability to allow system designs to protect various components from overheating situations. The PROCHOT# signal is bidirectional in that it can either signal when the processor has reached its maximum operating temperature or be driven from an external source to activate the TCC. The ability to activate the TCC using PROCHOT# can provide a means for thermal protection of system components.
