Datasheet

Datasheet, Volume 2 87
Processor Configuration Registers
2.6.1 VID—Vendor Identification Register
This register, combined with the Device Identification register, uniquely identify any PCI
device.
92–93h MC Message Control 0000h RW, RO
94–97h MA Message Address 00000000h RW, RO
98–99h MD Message Data 0000h RW
9A–9Fh RSVD Reserved 0h RO
A0–A1h PEG_CAPL PCI Express-G Capability List 0010h RO
A2–A3h PEG_CAP PCI Express-G Capabilities 0142h RO, RW-O
A4–A7h DCAP Device Capabilities 00008000h RO, RW-O
A8–A9h DCTL Device Control 0020h RO, RW
AA–ABh DSTS Device Status 0000h RW1C, RO
AC–AFh LCAP Link Capabilities
0261CD03h
RO, RO-V,
RW-O, RW-OV
B0–B1h LCTL Link Control 0000h RW, RO, RW-V
B2–B3h LSTS Link Status
1001h
RW1C, RO-V,
RO
B4–B7h SLOTCAP Slot Capabilities 00040000h RW-O, RO
B8–B9h SLOTCTL Slot Control 0000h RO
BA–BBh SLOTSTS Slot Status
0000h
RO, RW1C,
RO-V
BC–BDh RCTL Root Control 0000h RO, RW
BE–BFh RSVD Reserved 0h RO
C0–C3h RSTS Root Status
00000000h
RO, RW1C,
RO-V
C4–C7h DCAP2 Device Capabilities 2 00000800h RO, RW-O
C8–C9h DCTL2 Device Control 2 0000h RW-V, RW
CA–CBh RSVD Reserved 0h RO
CC–CFh LCAP2 Link Capabilities 2 0000000Eh RO-V
D0–D1h LCTL2 Link Control 2 0003h RWS, RWS-V
D2–D3h LSTS2 Link Status 2 0000h RO-V, RW1C
Table 2-9. PCI Device 1 Function 0–2 Configuration Space Register Address Map (Sheet 2
of 2)
Address
Offset
Register
Symbol
Register Name Reset Value Access
B/D/F/Type: 0/1/0–2/PCI
Address Offset: 0–1h
Reset Value: 8086h
Access: RO
Size: 16 bits
Bit Access
Reset
Value
RST/
PWR
Description
15:0 RO 8086h Uncore
Vendor Identification (VID)
PCI standard identification for Intel.